index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
stable-9.1
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
staging-9.1
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target-i386
/
ops_sse_header.h
Age
Commit message (
Expand
)
Author
Files
Lines
2016-01-21
target-i386: Rename struct XMMReg to ZMMReg
Eduardo Habkost
1
-40
/
+40
2013-04-13
target-i386: add AES-NI instructions
Aurelien Jarno
1
-0
/
+6
2013-04-13
target-i386: add pclmulqdq instruction
Aurelien Jarno
1
-0
/
+5
2012-08-14
x86: avoid AREG0 for FPU helpers
Blue Swirl
1
-167
/
+167
2010-06-16
tcg: Optionally sign-extend 32-bit arguments for 64-bit hosts.
Richard Henderson
1
-0
/
+3
2009-10-04
target-i386: add SSE4a instruction support
Andre Przywara
1
-0
/
+4
2009-07-16
Update to a hopefully more future proof FSF address
Blue Swirl
1
-2
/
+1
2009-01-04
Update FSF address in GPL/LGPL boilerplate
aurel32
1
-1
/
+1
2008-11-17
TCG variable type checking.
pbrook
1
-205
/
+211
2008-10-04
Implement SSE4.1, SSE4.2 (x86).
balrog
1
-1
/
+56
2008-09-25
Implement x86 SSSE3 instructions.
balrog
1
-1
/
+19
2008-05-22
proper helper definition registering (all targets must do that)
bellard
1
-164
/
+164
2008-05-15
converted more helpers to TCG - fixed some SVM issues
bellard
1
-1
/
+1
2008-05-12
converted SSE/MMX ops to TCG
bellard
1
-0
/
+264