riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2015-09-11	tlb: Add "ifetch" argument to cpu_mmu_index()	Benjamin Herrenschmidt	1	-1/+1
2015-09-08	target-cris: Use movcond and setcond	Richard Henderson	1	-10/+2
2015-03-13	tcg: Change translator-side labels to a pointer	Richard Henderson	1	-4/+2
2014-06-09	target-cris/translate.c: Remove t_gen_mov_TN_reg and t_gen_mov_reg_TN	Peter Maydell	1	-1/+1
2014-03-13	target-cris: Replace DisasContext::env field with CRISCPU	Andreas Färber	1	-8/+8
2014-03-13	exec: Change cpu_abort() argument to CPUState	Andreas Färber	1	-6/+6
2013-02-16	target-cris: Move TCG initialization to CRISCPU initfn	Andreas Färber	1	-4/+1
2012-09-15	target-cris: Switch to AREG0 free mode	Aurelien Jarno	1	-46/+49
2012-09-15	target-cris: Avoid AREG0 for helpers	Aurelien Jarno	1	-2/+2
2012-06-14	cris: Add break support for v10.	Edgar E. Iglesias	1	-0/+1
2012-03-14	target-cris: Don't overuse CPUState	Andreas Färber	1	-13/+13
2011-12-12	cris: Handle conditional stores on CRISv10	Stefan Sandstrom	1	-6/+66
2011-06-28	cris: Handle opcode zero	Edgar E. Iglesias	1	-3/+0
2011-05-08	Fix typo in comment (truely -> truly)	Stefan Weil	1	-1/+1
2011-01-10	cris: Allow more TB chaining for crisv10	Edgar E. Iglesias	1	-4/+6
2010-10-13	cris: avoid a write only variable	Blue Swirl	1	-3/+2
2010-03-18	Replace assert(0) with abort() or cpu_abort()	Blue Swirl	1	-7/+9
2010-03-07	Update to a hopefully more future proof FSF address	Blue Swirl	1	-2/+1
2010-02-20	cris: Mask interrupts on dslots for CRISv10.	Edgar E. Iglesias	1	-0/+4
2010-02-15	crisv10: Prettify.	Edgar E. Iglesias	1	-95/+91
2010-02-15	cris: Add support for CRISv10 translation.	Edgar E. Iglesias	1	-0/+1243