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AgeCommit message (Expand)AuthorFilesLines
2014-03-15misc: Fix typos in commentsStefan Weil1-1/+1
2014-03-13cputlb: Change tlb_set_page() argument to CPUStateAndreas Färber1-1/+1
2014-03-13cputlb: Change tlb_flush() argument to CPUStateAndreas Färber2-11/+30
2014-03-13cputlb: Change tlb_flush_page() argument to CPUStateAndreas Färber1-4/+10
2014-03-13exec: Change cpu_abort() argument to CPUStateAndreas Färber2-11/+26
2014-03-13translate-all: Change cpu_restore_state() argument to CPUStateAndreas Färber1-1/+1
2014-03-13cpu-exec: Change cpu_loop_exit() argument to CPUStateAndreas Färber1-4/+4
2014-03-13exec: Change tlb_fill() argument to CPUStateAndreas Färber1-5/+7
2014-03-13cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber3-5/+5
2014-03-13cpu: Move opaque field from CPU_COMMON to CPUStateAndreas Färber1-4/+5
2014-03-13cpu: Move exception_index field from CPU_COMMON to CPUStateAndreas Färber2-20/+25
2014-03-13cpu: Turn cpu_handle_mmu_fault() into a CPUClass hookAndreas Färber4-9/+16
2014-03-13cpu: Factor out cpu_generic_init()Andreas Färber1-13/+1
2014-03-13cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber2-6/+7
2014-03-13target-arm: Clean up ENV_GET_CPU() usageAndreas Färber1-5/+7
2014-03-10target-arm: Implement WFE as a yield operationPeter Maydell4-0/+18
2014-03-10target-arm: Fix intptr_t vs tcg_target_longRichard Henderson1-1/+1
2014-03-10target-arm: Implements the ARM PMCCNTR registerAlistair Francis2-4/+89
2014-03-10target-arm: Fix incorrect setting of E bit in CPSRPeter Maydell1-1/+1
2014-02-26target-arm: Add support for AArch32 ARMv8 CRC32 instructionsWill Newton5-0/+100
2014-02-26target-arm: Add utility function for checking AA32/64 state of an ELPeter Maydell1-0/+16
2014-02-26target-arm: Implement AArch64 view of CPACRPeter Maydell2-2/+3
2014-02-26target-arm: A64: Implement MSR (immediate) instructionsPeter Maydell3-1/+51
2014-02-26target-arm: Store AIF bits in env->pstate for AArch32Peter Maydell3-19/+30
2014-02-26target-arm: A64: Implement WFIPeter Maydell1-1/+4
2014-02-26target-arm: Get MMU index information correct for A64 codePeter Maydell2-4/+9
2014-02-26target-arm: Implement AArch64 OSLAR_EL1 sysreg as WIPeter Maydell1-0/+4
2014-02-26target-arm: Implement AArch64 dummy breakpoint and watchpoint registersPeter Maydell2-0/+36
2014-02-26target-arm: Implement AArch64 ID and feature registersPeter Maydell2-0/+55
2014-02-26target-arm: Implement AArch64 generic timersPeter Maydell2-14/+75
2014-02-26target-arm: Implement AArch64 MPIDRPeter Maydell1-2/+4
2014-02-26target-arm: Implement AArch64 TTBR*Peter Maydell2-63/+32
2014-02-26target-arm: Implement AArch64 VBAR_EL1Peter Maydell2-2/+9
2014-02-26target-arm: Implement AArch64 TCR_EL1Peter Maydell2-4/+17
2014-02-26target-arm: Implement AArch64 SCTLR_EL1Peter Maydell2-2/+3
2014-02-26target-arm: Implement AArch64 memory attribute registersPeter Maydell2-1/+26
2014-02-26target-arm: Implement AArch64 dummy MDSCR_EL1Peter Maydell1-0/+6
2014-02-26target-arm: Implement AArch64 TLB invalidate opsPeter Maydell1-0/+73
2014-02-26target-arm: Implement AArch64 cache invalidate/clean opsPeter Maydell2-2/+49
2014-02-26target-arm: Implement AArch64 MIDR_EL1Peter Maydell1-0/+3
2014-02-26target-arm: Implement AArch64 CurrentEL sysregPeter Maydell3-1/+12
2014-02-26target-arm: A64: Make cache ID registers visible to AArch64Peter Maydell4-11/+25
2014-02-26target-arm: Fix raw read and write functions on AArch64 registersPeter Maydell3-3/+15
2014-02-26arm: vgic device control api supportChristoffer Dall2-13/+59
2014-02-26target-arm: Load correct access bits from ARMv5 level 2 page table descriptorsPeter Maydell1-1/+1
2014-02-26target-arm: Fix incorrect arithmetic constructing short-form PAR for ATS opsPeter Maydell1-2/+2
2014-02-20target-arm: A64: Implement unprivileged load/storePeter Maydell1-32/+37
2014-02-20target-arm: A64: Implement narrowing three-reg-diff operationsPeter Maydell1-1/+59
2014-02-20target-arm: A64: Implement the wide 3-reg-different operationsPeter Maydell1-1/+40
2014-02-20target-arm: A64: Add most remaining three-reg-diff widening opsPeter Maydell1-21/+88
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