riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2014-02-26	target-arm: Implement AArch64 MPIDR	Peter Maydell	1	-2/+4
2014-02-26	target-arm: Implement AArch64 TTBR*	Peter Maydell	2	-63/+32
2014-02-26	target-arm: Implement AArch64 VBAR_EL1	Peter Maydell	2	-2/+9
2014-02-26	target-arm: Implement AArch64 TCR_EL1	Peter Maydell	2	-4/+17
2014-02-26	target-arm: Implement AArch64 SCTLR_EL1	Peter Maydell	2	-2/+3
2014-02-26	target-arm: Implement AArch64 memory attribute registers	Peter Maydell	2	-1/+26
2014-02-26	target-arm: Implement AArch64 dummy MDSCR_EL1	Peter Maydell	1	-0/+6
2014-02-26	target-arm: Implement AArch64 TLB invalidate ops	Peter Maydell	1	-0/+73
2014-02-26	target-arm: Implement AArch64 cache invalidate/clean ops	Peter Maydell	2	-2/+49
2014-02-26	target-arm: Implement AArch64 MIDR_EL1	Peter Maydell	1	-0/+3
2014-02-26	target-arm: Implement AArch64 CurrentEL sysreg	Peter Maydell	3	-1/+12
2014-02-26	target-arm: A64: Make cache ID registers visible to AArch64	Peter Maydell	4	-11/+25
2014-02-26	target-arm: Fix raw read and write functions on AArch64 registers	Peter Maydell	3	-3/+15
2014-02-26	arm: vgic device control api support	Christoffer Dall	2	-13/+59
2014-02-26	target-arm: Load correct access bits from ARMv5 level 2 page table descriptors	Peter Maydell	1	-1/+1
2014-02-26	target-arm: Fix incorrect arithmetic constructing short-form PAR for ATS ops	Peter Maydell	1	-2/+2
2014-02-20	target-arm: A64: Implement unprivileged load/store	Peter Maydell	1	-32/+37
2014-02-20	target-arm: A64: Implement narrowing three-reg-diff operations	Peter Maydell	1	-1/+59
2014-02-20	target-arm: A64: Implement the wide 3-reg-different operations	Peter Maydell	1	-1/+40
2014-02-20	target-arm: A64: Add most remaining three-reg-diff widening ops	Peter Maydell	1	-21/+88
2014-02-20	target-arm: A64: Add opcode comments to disas_simd_three_reg_diff	Peter Maydell	1	-11/+11
2014-02-20	target-arm: A64: Implement store-exclusive for system mode	Peter Maydell	1	-6/+62
2014-02-20	target-arm: Fix incorrect type for value argument to write_raw_cp_reg	Peter Maydell	1	-1/+1
2014-02-20	target-arm: Remove failure status return from read/write_raw_cp_reg	Peter Maydell	1	-24/+12
2014-02-20	target-arm: Remove unnecessary code now read/write fns can't fail	Peter Maydell	2	-6/+0
2014-02-20	target-arm: Drop success/fail return from cpreg read and write functions	Peter Maydell	4	-208/+137
2014-02-20	target-arm: Convert miscellaneous reginfo structs to accessfn	Peter Maydell	1	-25/+19
2014-02-20	target-arm: Convert generic timer reginfo to accessfn	Peter Maydell	1	-56/+66
2014-02-20	target-arm: Convert performance monitor reginfo to accessfn	Peter Maydell	1	-42/+28
2014-02-20	target-arm: Split cpreg access checks out from read/write functions	Peter Maydell	5	-4/+66
2014-02-20	target-arm: Stop underdecoding ARM946 PRBS registers	Peter Maydell	1	-23/+24
2014-02-20	target-arm: Log bad system register accesses with LOG_UNIMP	Peter Maydell	2	-1/+19
2014-02-20	target-arm: Remove unused ARMCPUState sr substruct	Peter Maydell	1	-5/+0
2014-02-20	target-arm: Restrict check_ap() use of S and R bits to v6 and earlier	Peter Maydell	1	-0/+3
2014-02-20	target-arm: Define names for SCTLR bits	Peter Maydell	3	-9/+61
2014-02-20	target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs	Peter Maydell	1	-1/+15
2014-02-20	target-arm: A64: Implement remaining 3-same instructions	Peter Maydell	5	-4/+130
2014-02-20	target-arm: A64: Implement floating point pairwise insns	Alex Bennée	1	-38/+86
2014-02-20	target-arm: A64: Implement SIMD FP compare and set insns	Alex Bennée	3	-12/+207
2014-02-20	target-arm: A64: Implement scalar three different instructions	Peter Maydell	1	-1/+94
2014-02-20	target-arm: A64: Implement SIMD scalar indexed instructions	Peter Maydell	1	-33/+82
2014-02-20	target-arm: A64: Implement long vector x indexed insns	Peter Maydell	1	-5/+139
2014-02-20	target-arm: A64: Implement plain vector SIMD indexed element insns	Peter Maydell	3	-1/+275
2014-02-11	exec: Make stl_*_phys input an AddressSpace	Edgar E. Iglesias	1	-1/+2
2014-02-11	exec: Make ldq/ldub_*_phys input an AddressSpace	Edgar E. Iglesias	1	-1/+2
2014-02-11	exec: Make ldl_*_phys input an AddressSpace	Edgar E. Iglesias	1	-6/+9
2014-02-08	disas: Implement disassembly output for A64	Claudio Fontana	1	-1/+1
2014-02-08	target-arm: Add support for AArch32 64bit VCVTB and VCVTT	Will Newton	1	-22/+61
2014-02-08	target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group	Peter Maydell	1	-3/+20
2014-02-08	target-arm: A64: Add 2-reg-misc REV* instructions	Alex Bennée	1	-1/+70