index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
stable-9.1
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
staging-9.1
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target-arm
/
translate.c
Age
Commit message (
Expand
)
Author
Files
Lines
2015-10-16
target-arm: Fix CPU breakpoint handling
Sergey Fedorov
1
-5
/
+14
2015-10-16
target-arm: Break the TB after ISB to execute self-modified code correctly
Sergey Sorokin
1
-2
/
+15
2015-10-07
tcg: Remove gen_intermediate_code_pc
Richard Henderson
1
-45
/
+9
2015-10-07
tcg: Pass data argument to restore_state_to_opc
Richard Henderson
1
-4
/
+5
2015-10-07
tcg: Add TCG_MAX_INSNS
Richard Henderson
1
-1
/
+5
2015-10-07
target-arm: Add condexec state to insn_start
Richard Henderson
1
-1
/
+2
2015-10-07
target-*: Introduce and use cpu_breakpoint_test
Richard Henderson
1
-15
/
+16
2015-10-07
target-*: Increment num_insns immediately after tcg_gen_insn_start
Richard Henderson
1
-3
/
+4
2015-10-07
target-*: Unconditionally emit tcg_gen_insn_start
Richard Henderson
1
-4
/
+1
2015-10-07
tcg: Rename debug_insn_start to insn_start
Richard Henderson
1
-1
/
+1
2015-09-14
target-arm: Handle always condition codes within arm_test_cc
Richard Henderson
1
-0
/
+9
2015-09-14
target-arm: Introduce DisasCompare
Richard Henderson
1
-46
/
+69
2015-09-14
target-arm: Share all common TCG temporaries
Richard Henderson
1
-5
/
+5
2015-09-11
maint: remove / fix many doubled words
Daniel P. Berrange
1
-1
/
+1
2015-09-08
target-arm: Fix default_exception_el() function for the case when EL3 is not ...
Sergey Sorokin
1
-1
/
+5
2015-08-24
tcg: Remove tcg_gen_trunc_i64_i32
Richard Henderson
1
-23
/
+23
2015-07-06
target-arm: Implement YIELD insn to yield in ARM and Thumb translators
Peter Maydell
1
-0
/
+7
2015-06-22
disas: Remove uses of CPU env
Peter Crosthwaite
1
-1
/
+1
2015-06-15
target-arm: Correct "preferred return address" for cpreg access exceptions
Peter Maydell
1
-1
/
+1
2015-06-15
target-arm: Add the THUMB_DSP feature
Aurelio C. Remonda
1
-10
/
+102
2015-05-29
target-arm: Avoid buffer overrun on UNPREDICTABLE ldrd/strd
Peter Maydell
1
-24
/
+32
2015-05-29
target-arm: Don't halt on WFI unless we don't have any work
Peter Maydell
1
-0
/
+4
2015-05-29
target-arm: Extend FP checks to use an EL
Greg Bellows
1
-10
/
+7
2015-05-29
target-arm: Add exception target el infrastructure
Greg Bellows
1
-23
/
+42
2015-03-16
target-arm: Fix handling of STM (user) with r15 in register list
Peter Maydell
1
-6
/
+12
2015-03-13
tcg: Change translator-side labels to a pointer
Richard Henderson
1
-4
/
+4
2015-02-12
tcg: Introduce tcg_op_buf_count and tcg_op_buf_full
Richard Henderson
1
-6
/
+3
2015-02-12
tcg: Move emit of INDEX_op_end into gen_tb_end
Richard Henderson
1
-1
/
+0
2015-02-05
target-arm: Use correct mmu_idx for unprivileged loads and stores
Peter Maydell
1
-2
/
+24
2015-02-05
target-arm: Define correct mmu_idx values and pass them in TB flags
Peter Maydell
1
-2
/
+3
2015-02-05
target-arm: check that LSB <= MSB in BFI instruction
Kirill Batuzov
1
-0
/
+4
2015-01-03
gen-icount: check cflags instead of use_icount global
Paolo Bonzini
1
-1
/
+1
2015-01-03
translate: check cflags instead of use_icount global
Paolo Bonzini
1
-2
/
+2
2014-12-11
target-arm: add secure state bit to CPREG hash
Peter Maydell
1
-5
/
+9
2014-12-11
target-arm: add non-secure Translation Block flag
Sergey Fedorov
1
-0
/
+1
2014-11-04
target-arm/translate.c: Don't pass CPUARMState * to disas_arm_insn()
Peter Maydell
1
-6
/
+5
2014-11-04
target-arm/translate.c: Don't pass CPUARMState around in the decoder
Peter Maydell
1
-44
/
+50
2014-11-04
target-arm/translate.c: Don't use IS_M()
Peter Maydell
1
-8
/
+11
2014-11-04
target-arm/translate.c: Use arm_dc_feature() rather than arm_feature()
Peter Maydell
1
-60
/
+80
2014-11-04
target-arm/translate.c: Use arm_dc_feature() in ENABLE_ARCH_ macros
Peter Maydell
1
-8
/
+8
2014-10-24
target-arm: rename arm_current_pl to arm_current_el
Greg Bellows
1
-2
/
+2
2014-10-24
target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0
Peter Maydell
1
-0
/
+3
2014-10-24
target-arm: Add support for A32 and T32 HVC and SMC insns
Peter Maydell
1
-11
/
+92
2014-09-29
target-arm: Don't handle c15_cpar changes via tb_flush()
Peter Maydell
1
-19
/
+21
2014-08-19
target-arm: Implement ARMv8 single-stepping for AArch32 code
Peter Maydell
1
-2
/
+74
2014-08-19
target-arm: Don't allow AArch32 to access RES0 CPSR bits
Peter Maydell
1
-6
/
+7
2014-08-12
trace: [tcg] Include TCG-tracing header on all targets
LluĂs Vilanova
1
-0
/
+3
2014-06-09
target-arm: Delete unused iwmmxt_msadb helper
Peter Maydell
1
-2
/
+0
2014-06-09
target-arm: A32/T32: Mask CRC value in calling code, not helper
Peter Maydell
1
-0
/
+10
2014-06-09
target-arm: add support for v8 VMULL.P64 instruction
Peter Maydell
1
-1
/
+25
[next]