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path: root/target-arm/helper.h
AgeCommit message (Expand)AuthorFilesLines
2016-02-11target-arm: Add isread parameter to CPAccessFnsPeter Maydell1-1/+1
2015-10-16target-arm: Fix CPU breakpoint handlingSergey Fedorov1-0/+2
2015-07-06target-arm: Split DISAS_YIELD from DISAS_WFEPeter Maydell1-0/+1
2015-05-29target-arm: Add exception target el infrastructureGreg Bellows1-1/+1
2014-09-29target-arm: A64: Emulate the SMC insnEdgar E. Iglesias1-0/+1
2014-09-29target-arm: A64: Emulate the HVC insnEdgar E. Iglesias1-0/+1
2014-08-19target-arm: Implement ARMv8 single-step handling for A64 codePeter Maydell1-0/+1
2014-06-09target-arm: Delete unused iwmmxt_msadb helperPeter Maydell1-2/+0
2014-06-09target-arm: add support for v8 VMULL.P64 instructionPeter Maydell1-0/+3
2014-06-09target-arm: add support for v8 SHA1 and SHA256 instructionsArd Biesheuvel1-0/+9
2014-05-28tcg: Invert the inclusion of helper.hRichard Henderson1-4/+0
2014-04-17target-arm: Implement AArch64 EL1 exception handlingRob Herring1-0/+1
2014-04-17target-arm: A64: Implement DC ZVAPeter Maydell1-0/+1
2014-04-17target-arm: Add support for generating exceptions with syndrome informationPeter Maydell1-1/+2
2014-04-17target-arm: Provide correct syndrome information for cpreg access trapsPeter Maydell1-1/+1
2014-03-18target-arm: A64: Add saturating accumulate ops (USQADD/SUQADD)Alex Bennée1-6/+14
2014-03-18target-arm: A64: Add saturating int ops (SQNEG/SQABS)Alex Bennée1-6/+8
2014-03-17target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)Alex Bennée1-2/+3
2014-03-17target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPEAlex Bennée1-2/+3
2014-03-10target-arm: Implement WFE as a yield operationPeter Maydell1-0/+1
2014-02-26target-arm: Add support for AArch32 ARMv8 CRC32 instructionsWill Newton1-0/+3
2014-02-26target-arm: A64: Implement MSR (immediate) instructionsPeter Maydell1-0/+2
2014-02-20target-arm: Split cpreg access checks out from read/write functionsPeter Maydell1-0/+1
2014-02-20target-arm: A64: Implement remaining 3-same instructionsPeter Maydell1-0/+2
2014-02-08target-arm: A64: Implement 2-reg-misc CNT, NOT and RBITPeter Maydell1-0/+1
2014-01-31target-arm: Add set_neon_rmode helperWill Newton1-0/+1
2014-01-08target-arm: A64: Add support for FCVT between half, single and doublePeter Maydell1-0/+2
2014-01-08target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructionsPeter Maydell1-0/+5
2014-01-08target-arm: A64: Add floating-point<->fixed-point instructionsAlexander Graf1-0/+2
2014-01-08target-arm: A64: Add extra VFP fixed point conversion helpersWill Newton1-0/+16
2014-01-08target-arm: Rename A32 VFP conversion helpersWill Newton1-8/+8
2014-01-08target-arm: Use VFP_BINOP macro for min, max, minnum, maxnumPeter Maydell1-7/+8
2013-12-17target-arm: A64: add stubs for a64 specific helpersAlexander Graf1-0/+4
2013-12-17target-arm: add support for v8 AES instructionsArd Biesheuvel1-0/+3
2013-12-10target-arm: Implement ARMv8 FP VMAXNM and VMINNM instructions.Will Newton1-0/+5
2013-10-10tcg: Remove stray semi-colons from target-*/helper.hRichard Henderson1-4/+4
2013-02-23target-arm: Implement sbc_cc inlineRichard Henderson1-2/+0
2013-02-23target-arm: Implement adc_cc inlineRichard Henderson1-1/+0
2013-02-23target-arm: Use mul[us]2 and add2 in umlal et alRichard Henderson1-2/+0
2012-12-19exec: move include files to include/exec/Paolo Bonzini1-2/+2
2012-10-28target-arm: rename helper flagsAurelien Jarno1-8/+8
2012-10-24target-arm: Implement abs_i32 inline rather than as a helperPeter Maydell1-1/+0
2012-10-24target-arm: Use TCG operation for Neon 64 bit negationPeter Maydell1-1/+0
2012-10-05target-arm: mark a few integer helpers const and pureAurelien Jarno1-9/+10
2012-10-05target-arm: convert sar, shl and shr helpers to TCGAurelien Jarno1-3/+0
2012-10-05target-arm: convert add_cc and sub_cc helpers to TCGAurelien Jarno1-2/+0
2012-09-15target-arm: convert remaining helpersBlue Swirl1-26/+26
2012-09-15target-arm: convert void helpersBlue Swirl1-4/+4
2012-06-20target-arm: Remove remaining old cp15 infrastructurePeter Maydell1-3/+0
2012-06-20target-arm: Convert TEECR, TEEHBR to new schemePeter Maydell1-2/+0
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