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target-arm
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helper.c
Age
Commit message (
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Author
Files
Lines
2015-04-26
Allow ARMv8 SCR.SMD updates
Greg Bellows
1
-1
/
+3
2015-04-26
target-arm: rename c1_coproc to cpacr_el1
Sergey Fedorov
1
-2
/
+2
2015-04-26
target-arm: Add user-mode transaction attribute
Peter Maydell
1
-0
/
+1
2015-04-26
target-arm: Use correct memory attributes for page table walks
Peter Maydell
1
-9
/
+40
2015-04-26
target-arm: Honour NS bits in page tables
Peter Maydell
1
-12
/
+67
2015-04-01
target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc)
Peter Maydell
1
-1
/
+1
2015-03-16
target-arm: Ignore low bit of PC in M-profile exception return
Peter Maydell
1
-0
/
+10
2015-03-16
target-arm: get_phys_addr_lpae: more xn control
Andrew Jones
1
-30
/
+100
2015-03-16
target-arm: fix get_phys_addr_v6/SCTLR_AFE access check
Andrew Jones
1
-7
/
+42
2015-03-16
target-arm: convert check_ap to ap_to_rw_prot
Andrew Jones
1
-30
/
+19
2015-02-13
target-arm: Add 32/64-bit register sync
Greg Bellows
1
-0
/
+211
2015-02-05
target-arm: fix for exponent comparison in recpe_f64
Ildar Isaev
1
-1
/
+1
2015-02-05
target-arm: Fix brace style in reindented code
Peter Maydell
1
-13
/
+23
2015-02-05
target-arm: Reindent ancient page-table-walk code
Peter Maydell
1
-96
/
+96
2015-02-05
target-arm: Use mmu_idx in get_phys_addr()
Peter Maydell
1
-51
/
+163
2015-02-05
target-arm: Pass mmu_idx to get_phys_addr()
Peter Maydell
1
-14
/
+96
2015-02-05
target-arm: Split AArch64 cases out of ats_write()
Peter Maydell
1
-7
/
+26
2015-02-05
target-arm: Define correct mmu_idx values and pass them in TB flags
Peter Maydell
1
-1
/
+2
2015-02-05
target-arm: Add checks that cpreg raw accesses are handled
Peter Maydell
1
-0
/
+31
2015-02-05
target-arm: Split NO_MIGRATE into ALIAS and NO_RAW
Peter Maydell
1
-104
/
+106
2015-02-05
target-arm: Add missing SP_ELx register definition
Greg Bellows
1
-0
/
+8
2015-02-05
target-arm: Add extended RVBAR support
Greg Bellows
1
-6
/
+25
2015-02-05
target-arm: Fix RVBAR_EL1 register encoding
Greg Bellows
1
-1
/
+1
2015-01-15
target-arm: Fix typo in comment (seperately -> separately)
Stefan Weil
1
-1
/
+1
2014-12-22
target-arm: Merge EL3 CP15 register lists
Greg Bellows
1
-31
/
+24
2014-12-11
target-arm: make MAIR0/1 banked
Greg Bellows
1
-3
/
+9
2014-12-11
target-arm: make c13 cp regs banked (FCSEIDR, ...)
Fabian Aggeler
1
-13
/
+45
2014-12-11
target-arm: make VBAR banked
Greg Bellows
1
-2
/
+3
2014-12-11
target-arm: make PAR banked
Fabian Aggeler
1
-10
/
+13
2014-12-11
target-arm: make IFAR/DFAR banked
Fabian Aggeler
1
-7
/
+9
2014-12-11
target-arm: make DFSR banked
Fabian Aggeler
1
-3
/
+4
2014-12-11
target-arm: make IFSR banked
Fabian Aggeler
1
-4
/
+9
2014-12-11
target-arm: make DACR banked
Fabian Aggeler
1
-10
/
+18
2014-12-11
target-arm: make TTBCR banked
Fabian Aggeler
1
-25
/
+47
2014-12-11
target-arm: make TTBR0/1 banked
Fabian Aggeler
1
-12
/
+25
2014-12-11
target-arm: make CSSELR banked
Fabian Aggeler
1
-3
/
+11
2014-12-11
target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI
Fabian Aggeler
1
-0
/
+54
2014-12-11
target-arm: add SCTLR_EL3 and make SCTLR banked
Fabian Aggeler
1
-30
/
+42
2014-12-11
target-arm: add MVBAR support
Fabian Aggeler
1
-6
/
+9
2014-12-11
target-arm: add SDER definition
Greg Bellows
1
-0
/
+8
2014-12-11
target-arm: add NSACR register
Fabian Aggeler
1
-0
/
+4
2014-12-11
target-arm: implement IRQ/FIQ routing to Monitor mode
Fabian Aggeler
1
-0
/
+9
2014-12-11
target-arm: move AArch32 SCR into security reglist
Fabian Aggeler
1
-6
/
+13
2014-12-11
target-arm: insert AArch32 cpregs twice into hashtable
Fabian Aggeler
1
-17
/
+81
2014-12-11
target-arm: add secure state bit to CPREG hash
Peter Maydell
1
-3
/
+4
2014-12-11
target-arm: add async excp target_el function
Greg Bellows
1
-19
/
+97
2014-11-17
target-arm: handle address translations that start at level 3
Peter Maydell
1
-9
/
+11
2014-10-24
target-arm: A32: Emulate the SMC instruction
Fabian Aggeler
1
-0
/
+11
2014-10-24
target-arm: rename arm_current_pl to arm_current_el
Greg Bellows
1
-11
/
+11
2014-10-24
target-arm: reject switching to monitor mode
Sergey Fedorov
1
-0
/
+2
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