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path: root/target-arm/helper.c
AgeCommit message (Expand)AuthorFilesLines
2015-02-13target-arm: Add 32/64-bit register syncGreg Bellows1-0/+211
2015-02-05target-arm: fix for exponent comparison in recpe_f64Ildar Isaev1-1/+1
2015-02-05target-arm: Fix brace style in reindented codePeter Maydell1-13/+23
2015-02-05target-arm: Reindent ancient page-table-walk codePeter Maydell1-96/+96
2015-02-05target-arm: Use mmu_idx in get_phys_addr()Peter Maydell1-51/+163
2015-02-05target-arm: Pass mmu_idx to get_phys_addr()Peter Maydell1-14/+96
2015-02-05target-arm: Split AArch64 cases out of ats_write()Peter Maydell1-7/+26
2015-02-05target-arm: Define correct mmu_idx values and pass them in TB flagsPeter Maydell1-1/+2
2015-02-05target-arm: Add checks that cpreg raw accesses are handledPeter Maydell1-0/+31
2015-02-05target-arm: Split NO_MIGRATE into ALIAS and NO_RAWPeter Maydell1-104/+106
2015-02-05target-arm: Add missing SP_ELx register definitionGreg Bellows1-0/+8
2015-02-05target-arm: Add extended RVBAR supportGreg Bellows1-6/+25
2015-02-05target-arm: Fix RVBAR_EL1 register encodingGreg Bellows1-1/+1
2015-01-15target-arm: Fix typo in comment (seperately -> separately)Stefan Weil1-1/+1
2014-12-22target-arm: Merge EL3 CP15 register listsGreg Bellows1-31/+24
2014-12-11target-arm: make MAIR0/1 bankedGreg Bellows1-3/+9
2014-12-11target-arm: make c13 cp regs banked (FCSEIDR, ...)Fabian Aggeler1-13/+45
2014-12-11target-arm: make VBAR bankedGreg Bellows1-2/+3
2014-12-11target-arm: make PAR bankedFabian Aggeler1-10/+13
2014-12-11target-arm: make IFAR/DFAR bankedFabian Aggeler1-7/+9
2014-12-11target-arm: make DFSR bankedFabian Aggeler1-3/+4
2014-12-11target-arm: make IFSR bankedFabian Aggeler1-4/+9
2014-12-11target-arm: make DACR bankedFabian Aggeler1-10/+18
2014-12-11target-arm: make TTBCR bankedFabian Aggeler1-25/+47
2014-12-11target-arm: make TTBR0/1 bankedFabian Aggeler1-12/+25
2014-12-11target-arm: make CSSELR bankedFabian Aggeler1-3/+11
2014-12-11target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFIFabian Aggeler1-0/+54
2014-12-11target-arm: add SCTLR_EL3 and make SCTLR bankedFabian Aggeler1-30/+42
2014-12-11target-arm: add MVBAR supportFabian Aggeler1-6/+9
2014-12-11target-arm: add SDER definitionGreg Bellows1-0/+8
2014-12-11target-arm: add NSACR registerFabian Aggeler1-0/+4
2014-12-11target-arm: implement IRQ/FIQ routing to Monitor modeFabian Aggeler1-0/+9
2014-12-11target-arm: move AArch32 SCR into security reglistFabian Aggeler1-6/+13
2014-12-11target-arm: insert AArch32 cpregs twice into hashtableFabian Aggeler1-17/+81
2014-12-11target-arm: add secure state bit to CPREG hashPeter Maydell1-3/+4
2014-12-11target-arm: add async excp target_el functionGreg Bellows1-19/+97
2014-11-17target-arm: handle address translations that start at level 3Peter Maydell1-9/+11
2014-10-24target-arm: A32: Emulate the SMC instructionFabian Aggeler1-0/+11
2014-10-24target-arm: rename arm_current_pl to arm_current_elGreg Bellows1-11/+11
2014-10-24target-arm: reject switching to monitor modeSergey Fedorov1-0/+2
2014-10-24target-arm: Correct sense of the DCZID DZP bitPeter Maydell1-1/+1
2014-10-24target-arm: add emulation of PSCI calls for system emulationRob Herring1-0/+6
2014-10-24target-arm: do not set do_interrupt handlers for ARM and AArch64 user modesRob Herring1-5/+0
2014-09-29target-arm: Add support for VIRQ and VFIQEdgar E. Iglesias1-0/+4
2014-09-29target-arm: Add IRQ and FIQ routing to EL2 and 3Edgar E. Iglesias1-0/+17
2014-09-29target-arm: A64: Emulate the SMC insnEdgar E. Iglesias1-0/+3
2014-09-29target-arm: Add a Hypervisor Trap exception typeEdgar E. Iglesias1-0/+1
2014-09-29target-arm: A64: Emulate the HVC insnEdgar E. Iglesias1-1/+19
2014-09-29target-arm: A64: Refactor aarch64_cpu_do_interruptEdgar E. Iglesias1-0/+13
2014-09-29target-arm: Add SCR_EL3Edgar E. Iglesias1-2/+33
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