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path: root/target-arm/helper.c
AgeCommit message (Expand)AuthorFilesLines
2016-01-18target-arm: Clean up includesPeter Maydell1-0/+1
2016-01-15target-arm: Use the right MMU index in arm_regime_using_lpae_formatAlvise Rigo1-4/+8
2015-12-17target-arm: raise exception on misaligned LDREX operandsAndrew Baumann1-0/+8
2015-11-24target-arm: Don't mask out bits [47:40] in LPAE descriptors for v8Peter Maydell1-1/+11
2015-11-03target-arm: Add and use symbolic names for register banksSoren Brinkmann1-15/+22
2015-10-27target-arm: Add support for S1 + S2 MMU translationsEdgar E. Iglesias1-7/+31
2015-10-27target-arm: Add S2 translation to 32bit S1 PTWsEdgar E. Iglesias1-5/+17
2015-10-27target-arm: Add S2 translation to 64bit S1 PTWsEdgar E. Iglesias1-2/+48
2015-10-27target-arm: Add ARMMMUFaultInfoEdgar E. Iglesias1-12/+20
2015-10-27target-arm: Avoid inline for get_phys_addrEdgar E. Iglesias1-8/+8
2015-10-27target-arm: Add support for S2 page-table protection bitsEdgar E. Iglesias1-4/+37
2015-10-27target-arm: Add computation of starting level for S2 PTWEdgar E. Iglesias1-13/+101
2015-10-27target-arm: lpae: Rename granule_sz to strideEdgar E. Iglesias1-15/+15
2015-10-27target-arm: lpae: Replace tsz with computed inputsizeEdgar E. Iglesias1-11/+11
2015-10-27target-arm: Add support for AArch32 S2 negative t0szEdgar E. Iglesias1-1/+17
2015-10-27target-arm: lpae: Move declaration of t0sz and t1szEdgar E. Iglesias1-2/+3
2015-10-27target-arm: lpae: Make t0sz and t1sz signed integersEdgar E. Iglesias1-2/+2
2015-10-27target-arm: Add HPFAR_EL2Edgar E. Iglesias1-0/+12
2015-10-27target-arm: Add support for SPSR_(ABT|UND|IRQ|FIQ)Soren Brinkmann1-0/+16
2015-10-16target-arm: Add MDCR_EL2Sergey Fedorov1-0/+12
2015-10-16target-arm: Implement AArch64 OSLAR/OSLSR_EL1 sysregsDavorin Mista1-2/+23
2015-10-16target-arm: Avoid calling arm_el_is_aa64() function for unimplemented ELSergey Sorokin1-2/+13
2015-10-16target-arm: Break the TB after ISB to execute self-modified code correctlySergey Sorokin1-1/+5
2015-10-16target-arm: Add missing 'static' attributeStefan Weil1-1/+1
2015-09-25arm: clarify the use of muldiv64()Laurent Vivier1-6/+8
2015-09-15target-arm: Use new revbit functionsRichard Henderson1-11/+1
2015-09-14target-arm: Add VMPIDR_EL2Edgar E. Iglesias1-2/+24
2015-09-14target-arm: Break out mpidr_read_val()Edgar E. Iglesias1-1/+6
2015-09-14target-arm: Add VPIDR_EL2Edgar E. Iglesias1-1/+41
2015-09-14target-arm: Suppress EPD for S2, EL2 and EL3 translationsEdgar E. Iglesias1-2/+4
2015-09-14target-arm: Suppress TBI for S2 translationsEdgar E. Iglesias1-1/+3
2015-09-14target-arm: Add VTTBR_EL2Edgar E. Iglesias1-2/+32
2015-09-14target-arm: Add VTCR_EL2Edgar E. Iglesias1-2/+41
2015-09-11tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt1-2/+2
2015-09-11maint: remove / fix many doubled wordsDaniel P. Berrange1-1/+1
2015-09-08target-arm: Add AArch64 access to PAR_EL1Edgar E. Iglesias1-0/+6
2015-09-08target-arm: Correct opc1 for AT_S12ExxEdgar E. Iglesias1-4/+4
2015-09-07target-arm: Fix AArch32:AArch64 general-purpose register mappingSergey Sorokin1-32/+32
2015-09-07arm: Remove hw_error() usages.Peter Crosthwaite1-1/+1
2015-09-07target-arm: Improve semihosting debug printsChristopher Covington1-3/+9
2015-08-25target-arm: Implement AArch64 TLBI operations on IPAsPeter Maydell1-0/+55
2015-08-25target-arm: Implement missing EL3 TLB invalidate operationsPeter Maydell1-0/+76
2015-08-25target-arm: Implement missing EL2 TLBI operationsPeter Maydell1-0/+22
2015-08-25target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touchPeter Maydell1-43/+129
2015-08-25target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric orderPeter Maydell1-8/+8
2015-08-25target-arm: Implement AArch32 ATS1H* operationsPeter Maydell1-0/+22
2015-08-25target-arm: Enable the AArch32 ATS12NSO opsPeter Maydell1-5/+11
2015-08-25target-arm: Wire up AArch64 EL2 and EL3 address translation opsPeter Maydell1-2/+41
2015-08-25target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translationsPeter Maydell1-0/+5
2015-08-25target-arm: Implement missing ACTLR registersPeter Maydell1-6/+15
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