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path: root/target-arm/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2015-09-07target-arm: Fix arm_excp_unmasked() functionSergey Sorokin1-3/+3
2015-09-07target-arm: Wire up HLT 0xf000 as the A64 semihosting instructionPeter Maydell1-0/+1
2015-09-07target-arm/arm-semi.c: Support widening APIs to 64 bitsPeter Maydell1-1/+1
2015-08-25target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3Peter Maydell1-0/+3
2015-08-13target-arm: Add the AArch64 view of the Secure physical timerPeter Maydell1-1/+2
2015-08-13target-arm: Add debug check for mismatched cpreg resetsPeter Maydell1-0/+3
2015-08-13target-arm: Add the Hypervisor timerEdgar E. Iglesias1-1/+2
2015-08-13target-arm: Add CNTHCTL_EL2Edgar E. Iglesias1-0/+1
2015-08-13target-arm: Add CNTVOFF_EL2Edgar E. Iglesias1-0/+1
2015-07-09cpu-exec: Purge all uses of ENV_GET_CPU()Peter Crosthwaite1-1/+1
2015-06-19target-arm: Implement PMSAv7 MPUPeter Crosthwaite1-0/+1
2015-06-19target-arm: Add registers for PMSAv7Peter Crosthwaite1-0/+10
2015-06-19target-arm: Do not reset sysregs marked as ALIASSergey Fedorov1-2/+2
2015-06-15target-arm: Add the THUMB_DSP featureAurelio C. Remonda1-0/+1
2015-06-15target-arm/cpu.h: remove pending_exceptionAlex Bennée1-1/+0
2015-05-29target-arm: Move TB flags down to fill gapPeter Maydell1-2/+2
2015-05-29target-arm: Extend FP checks to use an ELGreg Bellows1-22/+70
2015-05-29target-arm: Make singlestate TB flags common between AArch32/64Peter Maydell1-42/+27
2015-05-29target-arm: Add AArch64 CPTR registersGreg Bellows1-0/+5
2015-05-29target-arm: Allow cp access functions to indicate traps to EL2 or EL3Peter Maydell1-1/+5
2015-05-29target-arm: Update interrupt handling to use target ELGreg Bellows1-3/+4
2015-05-29target-arm: Move setting of exception info into tlb_fillPeter Maydell1-2/+0
2015-05-29target-arm: Add exception target el infrastructureGreg Bellows1-0/+1
2015-04-30tcg: Delete unused cpu_pc_from_tb()Peter Crosthwaite1-9/+0
2015-04-30arm: cpu.h: Remove unused typdefsPeter Crosthwaite1-5/+0
2015-04-26target-arm: rename c1_coproc to cpacr_el1Sergey Fedorov1-2/+2
2015-03-10cpu: Make cpu_init() return QOM CPUState objectEduardo Habkost1-8/+1
2015-02-13target-arm: Add 32/64-bit register syncGreg Bellows1-0/+2
2015-02-05target-arm: Guest cpu endianness determination for virtio KVM ARM/ARM64Pranavkumar Sawargaonkar1-0/+2
2015-02-05target-arm: Don't define any MMU_MODE*_SUFFIXesPeter Maydell1-2/+0
2015-02-05target-arm: Define correct mmu_idx values and pass them in TB flagsPeter Maydell1-23/+92
2015-02-05target-arm: Make arm_current_el() return sensible values for M profilePeter Maydell1-0/+4
2015-02-05target-arm: Split NO_MIGRATE into ALIAS and NO_RAWPeter Maydell1-4/+11
2015-01-20exec.c: Drop TARGET_HAS_ICE define and checksPeter Maydell1-2/+0
2014-12-11target-arm: make MAIR0/1 bankedGreg Bellows1-1/+20
2014-12-11target-arm: make c13 cp regs banked (FCSEIDR, ...)Fabian Aggeler1-5/+31
2014-12-11target-arm: make VBAR bankedGreg Bellows1-1/+9
2014-12-11target-arm: make PAR bankedFabian Aggeler1-1/+9
2014-12-11target-arm: make IFAR/DFAR bankedFabian Aggeler1-1/+18
2014-12-11target-arm: make DFSR bankedFabian Aggeler1-1/+9
2014-12-11target-arm: make IFSR bankedFabian Aggeler1-1/+9
2014-12-11target-arm: make DACR bankedFabian Aggeler1-2/+11
2014-12-11target-arm: make TTBCR bankedFabian Aggeler1-3/+8
2014-12-11target-arm: make TTBR0/1 bankedFabian Aggeler1-2/+18
2014-12-11target-arm: make CSSELR bankedFabian Aggeler1-1/+9
2014-12-11target-arm: add SCTLR_EL3 and make SCTLR bankedFabian Aggeler1-1/+9
2014-12-11target-arm: add MVBAR supportFabian Aggeler1-0/+1
2014-12-11target-arm: add SDER definitionGreg Bellows1-0/+1
2014-12-11target-arm: add NSACR registerFabian Aggeler1-0/+1
2014-12-11target-arm: add secure state bit to CPREG hashPeter Maydell1-5/+20
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