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path: root/target-arm/cpu-qom.h
AgeCommit message (Expand)AuthorFilesLines
2015-08-13target-arm: Add the AArch64 view of the Secure physical timerPeter Maydell1-0/+1
2015-08-13target-arm: Add the Hypervisor timerEdgar E. Iglesias1-0/+1
2015-06-19target-arm/helper.c: define MPUIR registerPeter Crosthwaite1-0/+2
2015-06-15arm: Add has-mpu propertyPeter Crosthwaite1-0/+3
2015-06-15arm: Implement uniprocessor with MP configPeter Crosthwaite1-0/+3
2015-06-15target-arm: Use the kernel's idea of MPIDR if we're using KVMPavel Fedin1-0/+1
2015-06-15target-arm: Fix REVIDR reset valueSergey Fedorov1-0/+1
2014-12-22target-arm: Add ARMCPU secure propertyGreg Bellows1-0/+2
2014-10-24target-arm: add emulation of PSCI calls for system emulationRob Herring1-0/+5
2014-10-24target-arm: add powered off cpu stateRob Herring1-0/+2
2014-09-25target-arm: Use cpu_exec_interrupt qom hookRichard Henderson1-0/+1
2014-08-19target-arm: Adjust debug ID registers per-CPUPeter Maydell1-0/+1
2014-07-08target-arm: Implement vCPU reset via KVM_ARM_VCPU_INIT for 32-bit CPUsPeter Maydell1-4/+0
2014-06-19target-arm: Introduce per-CPU field for PSCI versionPranavkumar Sawargaonkar1-0/+6
2014-06-19target-arm: Common kvm_arm_vcpu_init() for KVM ARM and KVM ARM64Pranavkumar Sawargaonkar1-0/+3
2014-04-17target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32Peter Maydell1-2/+0
2014-04-17target-arm: Implement CBAR for Cortex-A57Peter Maydell1-1/+1
2014-04-17target-arm: Implement RVBAR registerPeter Maydell1-0/+1
2014-04-17target-arm: Implement ARMv8 MVFR registersPeter Maydell1-0/+1
2014-04-17target-arm: Implement AArch64 EL1 exception handlingRob Herring1-0/+2
2014-04-17target-arm: A64: Implement DC ZVAPeter Maydell1-0/+2
2014-02-26target-arm: Implement AArch64 ID and feature registersPeter Maydell1-0/+10
2013-12-17ARM: cpu: add "reset_hivecs" propertyAntony Pavlov1-0/+1
2013-12-10target-arm: Don't hardcode KVM target CPU to be A15Peter Maydell1-0/+5
2013-12-10target-arm: Allow secondary KVM CPUs to be booted via PSCIPeter Maydell1-0/+3
2013-12-10target-arm: Add ARMCPU field for Linux device-tree 'compatible' stringPeter Maydell1-0/+3
2013-09-10target-arm: Add AArch64 gdbstub supportAlexander Graf1-0/+2
2013-09-10target-arm: Add AArch64 translation stubAlexander Graf1-0/+5
2013-09-10target-arm: Add new AArch64CPUInfo base class and subclassesPeter Maydell1-0/+12
2013-08-20target-arm: Implement the generic timerPeter Maydell1-0/+9
2013-07-27cpu: Introduce CPUClass::gdb_{read,write}_register()Andreas Färber1-0/+3
2013-07-23cpu: Turn cpu_get_phys_page_debug() into a CPUClass hookAndreas Färber1-0/+2
2013-07-09cpu: Drop unnecessary dynamic casts in *_env_get_cpu()Andreas Färber1-1/+1
2013-06-28cpu: Turn cpu_dump_{state,statistics}() into CPUState hooksAndreas Färber1-0/+3
2013-06-25target-arm: Reinitialize all KVM VCPU registers on resetPeter Maydell1-1/+5
2013-06-25target-arm: Convert TCG to using (index,value) list for cp migrationPeter Maydell1-0/+20
2013-04-19target-arm: port ARM CPU save/load to use VMStateJuan Quintela1-0/+4
2013-03-12target-arm: Override do_interrupt for ARMv7-M profileAndreas Färber1-0/+1
2013-03-12cpu: Replace do_interrupt() by CPUClass::do_interrupt methodAndreas Färber1-0/+2
2013-03-03cpu: Introduce ENV_OFFSET macrosAndreas Färber1-0/+2
2013-02-16target-arm: Update ARMCPU to QOM realizefnAndreas Färber1-1/+2
2012-12-19qom: move include files to include/qom/Paolo Bonzini1-1/+1
2012-06-20target-arm: Convert cp15 crn=1 registersPeter Maydell1-0/+1
2012-06-20target-arm: Add register_cp_regs_for_features()Peter Maydell1-0/+1
2012-06-20target-arm: initial coprocessor register frameworkPeter Maydell1-0/+3
2012-04-27target-arm: Move A9 config_base_address reset value to ARMCPUPeter Maydell1-0/+1
2012-04-27target-arm: Change cpu_arm_init() return type to ARMCPUAndreas Färber1-1/+0
2012-04-21target-arm: Move cache ID register setup to cpu specific init fnsPeter Maydell1-0/+5
2012-04-21target-arm: Move feature register setup to per-CPU init fnsPeter Maydell1-0/+14
2012-04-21target-arm: Move SCTLR reset value setup to per cpu init fnsPeter Maydell1-0/+1
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