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2021-09-13linux-user: Split linux-user internals out of qemu.hPeter Maydell2-0/+2
qemu.h is included in various non-linux-user files (which mostly want the TaskState struct and the functions for doing usermode access to guest addresses like lock_user(), unlock_user(), get_user*(), etc). Split out the parts that are only used in linux-user itself into a new user-internals.h. This leaves qemu.h with basically three things: * the definition of the TaskState struct * the user-access functions and macros * do_brk() all of which are needed by code outside linux-user that includes qemu.h. The addition of all the extra #include lines was done with sed -i '/include.*qemu\.h/a #include "user-internals.h"' $(git grep -l 'include.*qemu\.h' linux-user) (and then undoing the change to fpa11.h). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210908154405.15417-8-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-09-13linux-user: Split signal-related prototypes into signal-common.hPeter Maydell1-0/+1
Split the signal related prototypes into the existing header file signal-common.h, and include it in those places that now require it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210908154405.15417-4-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-07-13linux-user: update syscall.tbl to Linux v5.13Laurent Vivier1-6/+13
Updated running scripts/update-syscalltbl.sh Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210708215756.268805-4-laurent@vivier.eu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-07-13linux-user, mips: update syscall-args-o32.c.inc to Linux v5.13Laurent Vivier1-1/+4
Updated running scripts/update-mips-syscall-args.sh scripts/update-mips-syscall-args.sh has been updated to reflect file directory changes in strace repository. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210708215756.268805-3-laurent@vivier.eu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-07-12linux-user/mips: Move errno definitions to 'target_errno_defs.h'Philippe Mathieu-Daudé2-211/+215
Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210708170550.1846343-7-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-07-12linux-user: Extract target errno to 'target_errno_defs.h'Philippe Mathieu-Daudé1-0/+6
We want to access the target errno indepently of the rest of the linux-user code. Move the header containing the generic errno definitions ('errno_defs.h') to 'generic/target_errno_defs.h', create a new 'target_errno_defs.h' in each target which itself includes 'generic/target_errno_defs.h'. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210708170550.1846343-4-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-07-07linux-user/mips: Handle TARGET_EWOULDBLOCK as TARGET_EAGAINPhilippe Mathieu-Daudé1-0/+2
Linux kernel defines EWOULDBLOCK as EAGAIN (since before v2.6.12-rc2). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210704183755.655002-4-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-05-15linux-user: Pass CPUArchState to target_restore_altstackRichard Henderson1-1/+1
In most cases we were already passing get_sp_from_cpustate directly to the function. In other cases, we were passing a local variable which already contained the same value. In the rest of the cases, we were passing the stack pointer out of env directly. Reviewed by: Warner Losh <imp@bsdimp.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210426025334.1168495-5-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-05-15linux-user: Use target_restore_altstack in all sigreturnRichard Henderson1-5/+1
Note that target_restore_altstack uses the host memory pointer that we have already verified, so TARGET_EFAULT is not a possible return value. Note that using -EFAULT was a bug. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210426025334.1168495-3-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-02-13linux-user: target: signal: Support TARGET_SS_AUTODISARMChen Gang1-0/+6
Add definitions to pass building. Signed-off-by: Chen Gang <chengang@emindsoft.com.cn> Message-Id: <20201008043105.21058-1-chengang@emindsoft.com.cn> [lv: added the definitions in linux-user/generic/signal.h too] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-02-13linux-user: add TARGET_SO_{DOMAIN,PROTOCOL}Jason A. Donenfeld1-0/+2
These were defined for other platforms but mistakenly left out of mips and generic, so this commit adds them to the places missing. Then it makes them be translated in getsockopt. Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210204153925.2030606-1-Jason@zx2c4.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-01-14target/mips: Extract FPU helpers to 'fpu_helper.h'Philippe Mathieu-Daudé1-0/+1
Extract FPU specific helpers from "internal.h" to "fpu_helper.h". Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201120210844.2625602-2-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6Philippe Mathieu-Daudé1-1/+1
The MIPS ISA release 6 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-16-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2Philippe Mathieu-Daudé1-1/+1
The MIPS ISA release 2 is common to 32/64-bit CPUs. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-13-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6Philippe Mathieu-Daudé1-2/+1
Use the single ISA_MIPS32R6 definition to check if the Release 6 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R6 in few commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-11-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2Philippe Mathieu-Daudé1-1/+0
Use the single ISA_MIPS32R2 definition to check if the Release 2 ISA is supported, whether the CPU support 32/64-bit. For now we keep '32' in the definition name, we will rename it as ISA_MIPS_R2 in few commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-8-f4bug@amsat.org>
2020-11-15linux user: Fix Lesser GPL version numberChetan Pant2-2/+2
There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Message-Id: <20201023122455.19417-1-chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2020-11-11linux-user: Correct definition of stack_tLemonBoy1-3/+3
Some platforms used the wrong definition of stack_t where the flags and size fields were swapped or where the flags field had type ulong instead of int. Due to the presence of padding space in the structure and the prevalence of little-endian machines this problem went unnoticed for a long time. The type definitions have been cross-checked with the ones defined in the Linux kernel v5.9, plus some older versions for a few architecture that have been removed and Xilinx's kernel fork for NiosII [1]. The bsd-user headers remain unchanged as I don't know if they are wrong or not. [1] https://github.com/Xilinx/linux-xlnx/blob/master/arch/nios2/include/uapi/asm/signal.h Signed-off-by: Giuseppe Musacchio <thatlemon@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <e9d47692-ee92-009f-6007-0abc3f502b97@gmail.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-11-04linux-user/mips/cpu_loop: silence the compiler warningsChen Qun1-0/+4
When using -Wimplicit-fallthrough in our CFLAGS, the compiler showed warning: linux-user/mips/cpu_loop.c: In function ‘cpu_loop’: linux-user/mips/cpu_loop.c:104:24: warning: this statement may fall through [-Wimplicit-fallthrough=] 104 | if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) { | ^ linux-user/mips/cpu_loop.c:107:17: note: here 107 | case 7: | ^~~~ linux-user/mips/cpu_loop.c:108:24: warning: this statement may fall through [-Wimplicit-fallthrough=] 108 | if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) { | ^ linux-user/mips/cpu_loop.c:111:17: note: here 111 | case 6: | ^~~~ linux-user/mips/cpu_loop.c:112:24: warning: this statement may fall through [-Wimplicit-fallthrough=] 112 | if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) { | ^ linux-user/mips/cpu_loop.c:115:17: note: here 115 | case 5: | ^~~~ Add the corresponding "fall through" comment to fix it. Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20201030004046.2191790-5-kuhn.chenqun@huawei.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-10-26linux-user: update syscall.tbl to Linux 5.9-rc7Laurent Vivier1-3/+5
Updated running scripts/update-syscalltbl.sh Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200930003033.554124-4-laurent@vivier.eu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-10-26linux-user: update mips/syscall-args-o32.c.inc to Linux 5.9-rc7Laurent Vivier1-0/+4
Updated running scripts/update-mips-syscall-args.sh Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200930003033.554124-3-laurent@vivier.eu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-08-27linux-user: Add missing termbits types and values definitionsFilip Bozuta1-6/+11
This patch introduces missing target types ('target_flag_t', 'target_cc_t', 'target_speed_t') in a few 'termibts.h' header files. Also, two missing values ('TARGET_IUTF8' and 'TARGET_EXTPROC') were also added. These values were also added in file 'syscall.c' in bitmask tables 'iflag_tbl[]' and 'lflag_tbl[]' which are used to convert values of 'struct termios' between target and host. Signed-off-by: Filip Bozuta <Filip.Bozuta@syrmia.com> Reviewed-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20200723210233.349690-3-Filip.Bozuta@syrmia.com> [lv: keep TARGET_NCCS definition in xtensa/termbits.h] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-08-27linux-user: Add strace support for printing arguments of syscalls used to ↵Filip Bozuta1-2/+3
lock and unlock memory This patch implements strace argument printing functionality for following syscalls: * mlock, munlock, mlockall, munlockall - lock and unlock memory int mlock(const void *addr, size_t len) int munlock(const void *addr, size_t len) int mlockall(int flags) int munlockall(void) man page: https://man7.org/linux/man-pages/man2/mlock.2.html Implementation notes: Syscall mlockall() takes an argument that is composed of predefined values which represent flags that determine the type of locking operation that is to be performed. For that reason, a printing function "print_mlockall" was stated in file "strace.list". This printing function uses an already existing function "print_flags()" to print the "flags" argument. These flags are stated inside an array "mlockall_flags" that contains values of type "struct flags". These values are instantiated using an existing macro "FLAG_TARGET()" that crates aproppriate target flag values based on those defined in files '/target_syscall.h'. These target flag values were changed from "TARGET_MLOCKALL_MCL*" to "TARGET_MCL_*" so that they can be aproppriately set and recognised in "strace.c" with "FLAG_TARGET()". Value for "MCL_ONFAULT" was added in this patch. This value was also added in "syscall.c" in function "target_to_host_mlockall_arg()". Because this flag value was added in kernel version 4.4, it is enwrapped in an #ifdef directive (both in "syscall.c" and in "strace.c") as to support older kernel versions. The other syscalls have only primitive argument types, so the rest of the implementation was handled by stating an appropriate printing format in file "strace.list". Syscall mlock2() is not implemented in "syscall.c" and thus it's argument printing is not implemented in this patch. Signed-off-by: Filip Bozuta <Filip.Bozuta@syrmia.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20200811164553.27713-4-Filip.Bozuta@syrmia.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-08-21meson: linux-userMarc-André Lureau3-5/+7
The most interesting or most complicated part here is the syscall_nr.h generators. In order to keep the generation logic all in meson.build, I am adding to config_target the name of the .tbl file, and making the generated file syscall<SUFFIX>_nr.h for input file syscall<SUFFIX>.tbl. For architectures where the input file is not named syscall_nr.tbl, syscall_nr.h has to be a source file; it's just a forwarder for x86 (i386/x86_64), while for MIPS64 it chooses between N32 and N64 ABIs. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-03-20linux-user,mips: update syscall-args-o32.c.incLaurent Vivier1-438/+436
Add a script to update the file from strace github and run it Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20200310103403.3284090-22-laurent@vivier.eu> [lv: added file in MAINTAINERS] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-03-20linux-user,mips: move content of mips_syscall_argsLaurent Vivier2-439/+439
Move content of mips_syscall_args to mips-syscall-args-o32.c.inc to ease automatic update. No functionnal change Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20200310103403.3284090-21-laurent@vivier.eu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-03-20linux-user: update syscall.tbl from linux 0bf999f9c5e7Laurent Vivier1-0/+2
Run scripts/update-syscalltbl.sh with linux commit 0bf999f9c5e7 Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20200310103403.3284090-20-laurent@vivier.eu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-03-20linux-user, mips: add syscall table generation supportLaurent Vivier4-425/+466
Copy syscall.tbl and syscallhdr.sh from linux/arch/mips/kernel/syscalls/syscall_o32.tbl v5.5 Update syscallhdr.sh to generate QEMU syscall_nr.h Move the offset (4000) from the file to the Makefile.objs to be passed to syscallhdr.sh Rename on the fly fadvise64 to fadvise64_64. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20200310103403.3284090-17-laurent@vivier.eu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-02-17linux-user: mips: Update syscall numbers to kernel 5.5 levelAleksandar Markovic2-1/+127
Update mips syscall numbers based on Linux kernel tag v5.5. CC: Aurelien Jarno <aurelien@aurel32.net> CC: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <1581596954-2305-6-git-send-email-aleksandar.markovic@rt-rk.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-11-06linux-user: Introduce cpu_clone_regs_parentRichard Henderson1-0/+4
We will need a target-specific hook for adjusting registers in the parent during clone. Add an empty inline function for each target, and invoke it from the proper places. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20191106113318.10226-11-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-11-06linux-user: Rename cpu_clone_regs to cpu_clone_regs_childRichard Henderson1-1/+2
We will need a target-specific hook for adjusting registers in the parent during clone. To avoid confusion, rename the one we have to make it clear it affects the child. At the same time, pass in the flags from the clone syscall. We will need them for correct behaviour for Sparc. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20191106113318.10226-10-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-08-19target/mips: rationalise softfloat includesAlex Bennée1-0/+1
We should avoid including the whole of softfloat headers in cpu.h and explicitly include it only where we will be calling softfloat functions. We can use the -types.h in cpu.h for the few bits that are global. We also move the restore_snan_bit_mode into internal.h and include -helpers.h there. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-07-16linux-user: Fix structure target_ucontext for MIPSAleksandar Markovic1-3/+2
Structure ucontext for MIPS is defined in the following way in Linux kernel: (arch/mips/include/uapi/asm/ucontext.h, lines 54-64) struct ucontext { /* Historic fields matching asm-generic */ unsigned long uc_flags; struct ucontext *uc_link; stack_t uc_stack; struct sigcontext uc_mcontext; sigset_t uc_sigmask; /* Extended context structures may follow ucontext */ unsigned long long uc_extcontext[0]; }; Fix the structure target_ucontext for MIPS to reflect the definition above, except the correction for field uc_extcontext, which will follow at some later time. Fixes: 94c5495d Reported-by: Dragan Mladjenovic <dmladjenovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <1562931470-3700-2-git-send-email-aleksandar.markovic@rt-rk.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-07-02linux-user: Handle EXCP_FPE properly for MIPSAleksandar Markovic1-0/+17
Handle EXCP_FPE properly for MIPS in cpu loop. Note that a vast majority of FP instructions are not affected by the absence of the code in this patch, as they use alternative code paths for handling floating point exceptions (see, for example, invocations of update_fcr31()) - they rely on softfloat library for keeping track on exceptions that needs to be raised. However, there are few MIPS FP instructions (an example is CTC1) that use function do_raise_exception() directly, and they need the case that is added in this patch to propagate the FPE exception as designed. The code is based on kernel's function force_fcr31_sig() in arch/mips/kernel.traps.c. Reported-by: Yunqiang Su <ysu@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <1561718618-20218-6-git-send-email-aleksandar.markovic@rt-rk.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-07-02linux-user: Introduce TARGET_HAVE_ARCH_STRUCT_FLOCKAleksandar Markovic1-4/+13
Bring target_flock definitions to be more in sync with the way flock is defined in kernel. Basically, the rules from the kernel are: 1. Majority of architectures have a common flock definition. 2. Architectures with 32-bit MIPS ABIs have a sligtly different flock definition; those architectures are the only arcitectures that have HAVE_ARCH_STRUCT_FLOCK defined, and that preprocessor constant is used in the common header as a flag for including or not including common flock definition. 3. Sparc architectures also have a sligtly different flock definition, but the difference is only the padding at the end of the structure. The presence of that padding is determined by preprocessor constants __ARCH_FLOCK6_PAD and __ARCH_FLOCK64_PAD. QEMU linux-user already implements rules 1. and 3. in a very similar way as they are implemented in kernel. However, rule 2. is implemented in a dissimilar way (for example, the constant TARGET_HAVE_ARCH_STRUCT_FLOCK is missing), and this patch brings QEMU implementation much closer to the kernel implementation. TARGET_HAVE_ARCH_STRUCT_FLOCK64 constant is also introduced to mimic HAVE_ARCH_STRUCT_FLOCK64 from kernel, but it is not defined anywhere, however, this is the case with HAVE_ARCH_STRUCT_FLOCK64 in kernel as well. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <1561718618-20218-5-git-send-email-aleksandar.markovic@rt-rk.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-07-02linux-user: Fix target_flock structure for MIPS O64 ABIAleksandar Markovic1-0/+4
Among MIPS ABIs, only MIPS O32 and N32 have special (different than other architectures) definition of structure flock in kernel. Bring target_flock definition in QEMU for MIPS O64 ABI to the correct state, which is currently different than the most common definition, and it should actually be the same. Reported-by: Dragan Mladjenovic <dmladjenovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <1561718618-20218-4-git-send-email-aleksandar.markovic@rt-rk.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-06-12Supply missing header guardsMarkus Armbruster2-0/+11
Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190604181618.19980-5-armbru@redhat.com>
2019-06-12Include qemu-common.h exactly where neededMarkus Armbruster1-0/+1
No header includes qemu-common.h after this commit, as prescribed by qemu-common.h's file comment. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190523143508.25387-5-armbru@redhat.com> [Rebased with conflicts resolved automatically, except for include/hw/arm/xlnx-zynqmp.h hw/arm/nrf51_soc.c hw/arm/msf2-soc.c block/qcow2-refcount.c block/qcow2-cluster.c block/qcow2-cache.c target/arm/cpu.h target/lm32/cpu.h target/m68k/cpu.h target/mips/cpu.h target/moxie/cpu.h target/nios2/cpu.h target/openrisc/cpu.h target/riscv/cpu.h target/tilegx/cpu.h target/tricore/cpu.h target/unicore32/cpu.h target/xtensa/cpu.h; bsd-user/main.c and net/tap-bsd.c fixed up]
2019-06-10target/mips: Use env_cpu, env_archcpuRichard Henderson1-1/+1
Cleanup in the boilerplate that each target must define. Replace mips_env_get_cpu with env_archcpu. The combination CPU(mips_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-10cpu: Replace ENV_GET_CPU with env_cpuRichard Henderson1-1/+1
Now that we have both ArchCPU and CPUArchState, we can define this generically instead of via macro in each target's cpu.h. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-14target/mips: reimplement SC instruction emulation and use cmpxchgLeon Alrae1-73/+0
Completely rewrite conditional stores handling. Use cmpxchg. This eliminates need for separate implementations of SC instruction emulation for user and system emulation. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Acked-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-11-12linux-user: Don't call gdb_handlesig() before queue_signal()Peter Maydell1-12/+4
The CPU main-loop routines for linux-user generally call gdb_handlesig() when they're about to queue a SIGTRAP signal. This is wrong, because queue_signal() will cause us to pend a signal, and process_pending_signals() will then call gdb_handlesig() itself. So the effect is that we notify gdb of the SIGTRAP, and then if gdb says "OK, continue with signal X" we will incorrectly notify gdb of the signal X as well. We don't do this double-notify for anything else, only SIGTRAP. Remove this unnecessary and incorrect code from all the targets except for nios2 (whose main loop is doing something different and broken, and will be handled in a separate patch). This bug only manifests if the user responds to the reported SIGTRAP using "signal SIGFOO" rather than "continue"; since the latter is the overwhelmingly common thing to do after a breakpoint most people won't have hit this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20181019174958.26616-2-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-10-29linux-user: Add prctl() PR_SET_FP_MODE and PR_GET_FP_MODE implementationsStefan Markovic1-0/+2
Implement MIPS specific prctl() PR_SET_FP_MODE and PR_GET_FP_MODE emulation. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-10-29linux-user: Determine the desired FPU mode from MIPS.abiflagsStefan Markovic1-0/+75
Floating-point mode is calculated from MIPS.abiflags FP ABI value (based on kernel implementation). Illegal combinations are rejected. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-10-24linux-user/mips: Recognize the R5900 CPU modelFredrik Noring1-0/+3
This kind of ELF for the R5900 relies on an IEEE 754-1985 compliant FPU. The R5900 FPU hardware is noncompliant and it is therefore emulated in software by the Linux kernel. QEMU emulates a compliant FPU accordingly. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-18linux-user: Add MIPS-specific prctl() optionsStefan Markovic1-0/+4
Add MIPS-specific prctl() options TARGET_PR_SET_FP_MODE and TARGET_PR_SET_FP_MODE. These values are essentially copied from linux kernel header include/uapi/linux/prctl.h. This is done in a way consistent with a similar case of aarch64-specific prctl() options TARGET_PR_SVE_SET_VL and TARGET_PR_SVE_GET_VL. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-08-24elf: Don't check FCR31_NAN2008 bit for nanoMIPSAleksandar Markovic1-0/+3
nanoMIPS is always NaN2008 compliant, and rules for checking FCR31's NAN2008 bit are obsoleted. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-24target/mips: Implement emulation of nanoMIPS LLWP/SCWP pairAleksandar Rikalo1-5/+20
Implement support for nanoMIPS LLWP/SCWP instructions. Beside adding core functionality of these instructions, this patch adds support for availability control via configuration bit XNP. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Dimitrije Nikolic <dnikolic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-08-16linux-user: Update MIPS syscall numbers up to kernel 4.18 headersAleksandar Markovic1-0/+9
Synchronize content of linux-user/mips/syscall_nr.h and linux-user/mips64/syscall_nr.h with Linux kernel 4.18 headers. This adds 9 new syscall numbers, the last being NR_io_pgetevents. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
2018-06-04linux-user: move mips signal definitions to mips/target_signal.hLaurent Vivier1-0/+50
No code change. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180529194207.31503-12-laurent@vivier.eu>
generated by cgit v1.1 at 2024-11-03 09:32:44 +0000