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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-12-16 12:06:51 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-01-14 17:13:53 +0100 |
| commit | f395cef7656e794a5c6c007bdf661603410640d8 (patch) | |
| tree | f94e78513a1e74de7946ed1e32e2fcaebcd43b9c /linux-user/mips | |
| parent | 08e2262fada2de06232e8099bddf6e03df015c5a (diff) | |
| download | qemu-f395cef7656e794a5c6c007bdf661603410640d8.zip qemu-f395cef7656e794a5c6c007bdf661603410640d8.tar.gz qemu-f395cef7656e794a5c6c007bdf661603410640d8.tar.bz2 | |
target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2
Use the single ISA_MIPS32R2 definition to check if the Release 2
ISA is supported, whether the CPU support 32/64-bit.
For now we keep '32' in the definition name, we will rename it
as ISA_MIPS_R2 in few commits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210104221154.3127610-8-f4bug@amsat.org>
Diffstat (limited to 'linux-user/mips')
| -rw-r--r-- | linux-user/mips/cpu_loop.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index cfe7ba5..f083137 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -385,7 +385,6 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) prog_req.fre &= interp_req.fre; bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS32R2 || - env->insn_flags & ISA_MIPS64R2 || env->insn_flags & ISA_MIPS32R6 || env->insn_flags & ISA_MIPS64R6; |