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2024-12-20hw/riscv: add riscv-iommu-sys platform deviceTomasz Jeznach1-0/+4
This device models the RISC-V IOMMU as a sysbus device. The same design decisions taken in the riscv-iommu-pci device were kept, namely the existence of 4 vectors are available for each interrupt cause. The WSIs are emitted using the input of the s->notify() callback as a index to an IRQ list. The IRQ list starts at 'base_irq' and goes until base_irq + 3. This means that boards must have 4 contiguous IRQ lines available, starting from 'base_irq'. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241106133407.604587-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-12-19hw/core/qdev-properties: Constify Property argument to PropertyInfo.printRichard Henderson1-1/+1
This logically should have accompanied d36f165d952 which allowed const Property to be registered. There is exactly one instance of this method: print_pci_devfn. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Lei Yang <leiyang@redhat.com> Link: https://lore.kernel.org/r/20241218134251.4724-24-richard.henderson@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-12-19hw/core/qdev-properties: Constify Property argument to object_field_prop_ptrRichard Henderson1-1/+1
This logically should have accompanied d36f165d952 which allowed const Property to be registered. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Lei Yang <leiyang@redhat.com> Link: https://lore.kernel.org/r/20241218134251.4724-23-richard.henderson@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-12-19include/hw/qdev-properties: Shrink struct PropertyRichard Henderson1-4/+4
Before, via pahole: arm32, a 32-bit host which aligns uint64_t: struct Property { const char * name; /* 0 4 */ const PropertyInfo * info; /* 4 4 */ ptrdiff_t offset; /* 8 4 */ uint8_t bitnr; /* 12 1 */ /* XXX 3 bytes hole, try to pack */ uint64_t bitmask; /* 16 8 */ _Bool set_default; /* 24 1 */ /* XXX 7 bytes hole, try to pack */ union { int64_t i; /* 32 8 */ uint64_t u; /* 32 8 */ } defval; /* 32 8 */ int arrayoffset; /* 40 4 */ const PropertyInfo * arrayinfo; /* 44 4 */ int arrayfieldsize; /* 48 4 */ const char * link_type; /* 52 4 */ /* size: 56, cachelines: 1, members: 11 */ /* sum members: 46, holes: 2, sum holes: 10 */ }; arm64, an arbitrary 64-bit host: struct Property { const char * name; /* 0 8 */ const PropertyInfo * info; /* 8 8 */ ptrdiff_t offset; /* 16 8 */ uint8_t bitnr; /* 24 1 */ /* XXX 7 bytes hole, try to pack */ uint64_t bitmask; /* 32 8 */ _Bool set_default; /* 40 1 */ /* XXX 7 bytes hole, try to pack */ union { int64_t i; /* 48 8 */ uint64_t u; /* 48 8 */ } defval; /* 48 8 */ int arrayoffset; /* 56 4 */ /* XXX 4 bytes hole, try to pack */ const PropertyInfo * arrayinfo; /* 64 8 */ int arrayfieldsize; /* 72 4 */ /* XXX 4 bytes hole, try to pack */ const char * link_type; /* 80 8 */ /* size: 88, cachelines: 2, members: 11 */ /* sum members: 66, holes: 4, sum holes: 22 */ }; Afterward there are no holes in either structure. For arm32, size 48, padding 2, saved 8 bytes. For arm64, size 72, padding 6, saved 16 bytes. Saves 20k from qemu-system-aarch64 on a 64-bit host. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Lei Yang <leiyang@redhat.com> Link: https://lore.kernel.org/r/20241218134251.4724-22-richard.henderson@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-12-19include/hw/qdev-properties: Remove DEFINE_PROP_END_OF_LISTRichard Henderson2-10/+7
Now that all of the Property arrays are counted, we can remove the terminator object from each array. Update the assertions in device_class_set_props to match. With struct Property being 88 bytes, this was a rather large form of terminator. Saves 30k from qemu-system-aarch64. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Lei Yang <leiyang@redhat.com> Link: https://lore.kernel.org/r/20241218134251.4724-21-richard.henderson@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-12-19hw/core: Remove device_class_set_props functionRichard Henderson1-10/+6
All uses of device_class_set_props() are now using arrays. Validate this compile-time in the device_class_set_props macro and call device_class_set_props_n using the known size of the array. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Lei Yang <leiyang@redhat.com> Link: https://lore.kernel.org/r/20241218134251.4724-19-richard.henderson@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-12-19hw/core: Introduce device_class_set_props_nRichard Henderson1-0/+18
Record the size of the array in DeviceClass.props_count_. Iterate with known count in qdev_prop_walk. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Lei Yang <leiyang@redhat.com> Link: https://lore.kernel.org/r/20241218134251.4724-14-richard.henderson@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-12-19include/hw/qdev-core: Detect most empty Property lists at compile timeRichard Henderson1-0/+17
Add a macro expansion of device_class_set_props which can check on the type and size of PROPS before calling the function. Avoid the macro in migration.c because migration_properties is defined externally with indeterminate size. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Lei Yang <leiyang@redhat.com> Link: https://lore.kernel.org/r/20241218134251.4724-13-richard.henderson@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-12-19hw/intc/loongarch_extioi: Code cleanup about loongarch_extioiBibo Mao1-2/+0
Remove definition about LoongArchExtIOI and LOONGARCH_EXTIOI, and replace them with LoongArchExtIOICommonState and macro LOONGARCH_EXTIOI_COMMON separately. Also remove unnecessary header files. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2024-12-19hw/intc/loongarch_extioi: Add pre_save interfaceBibo Mao1-0/+1
Add vmstate pre_save interface, which can be used extioi kvm driver in future. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2024-12-19hw/intc/loongarch_extioi: Inherit from loongarch_extioi_commonBibo Mao2-2/+27
Set TYPE_LOONGARCH_EXTIOI inherit from TYPE_LOONGARCH_EXTIOI_COMMON object, it shares vmsate and property of TYPE_LOONGARCH_EXTIOI_COMMON, and has its own realize() function. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2024-12-19include: Rename LoongArchExtIOI with LoongArchExtIOICommonStateBibo Mao2-1/+2
Rename structure LoongArchExtIOI with LoongArchExtIOICommonState, since it is defined in file loongarch_extioi_common.h Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2024-12-19include: Move struct LoongArchExtIOI to header file loongarch_extioi_commonBibo Mao2-26/+27
Move definiton of structure LoongArchExtIOI from header file loongarch_extioi.h to file loongarch_extioi_common.h. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2024-12-19include: Add loongarch_extioi_common header fileBibo Mao2-49/+59
Add common header file include/hw/intc/loongarch_extioi_common.h, and move some macro definition from include/hw/intc/loongarch_extioi.h to the common header file. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2024-12-19hw/intc/loongarch_pch: Code cleanup about loongarch_pch_picBibo Mao1-4/+0
Remove definition about LoongArchPCHPIC and LOONGARCH_PCH_PIC, and replace them with LoongArchPICCommonState and LOONGARCH_PIC_COMMON separately. Also remove unnecessary header files. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2024-12-19hw/intc/loongarch_pch: Add pre_save and post_load interfacesBibo Mao1-0/+2
Add vmstate pre_save and post_load interfaces, which can be used by pic kvm driver in future. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2024-12-19hw/intc/loongarch_pch: Inherit from loongarch_pic_commonBibo Mao2-4/+27
Set TYPE_LOONGARCH_PIC inherit from TYPE_LOONGARCH_PIC_COMMON object, it shares vmsate and property of TYPE_LOONGARCH_PIC_COMMON, and has its own realize() function. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2024-12-19include: Move struct LoongArchPCHPIC to loongarch_pic_common header fileBibo Mao2-26/+29
Move structure LoongArchPCHPIC from header file loongarch_pch_pic.h to file loongarch_pic_common.h, and rename structure name with LoongArchPICCommonState. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2024-12-19include: Add loongarch_pic_common header fileBibo Mao2-31/+47
Add common header file hw/intc/loongarch_pic_common.h, and move some macro definition from hw/intc/loongarch_pch_pic.h to the common header file. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
2024-12-16x86/loader: add -shim optionGerd Hoffmann1-0/+1
Add new -shim command line option, wire up for the x86 loader. When specified load shim into the new "etc/boot/shim" fw_cfg file. Needs OVMF changes too to be actually useful. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-ID: <20240905141211.1253307-6-kraxel@redhat.com>
2024-12-14hw/ide/ahci: Decouple from PCIBernhard Beschow2-2/+2
In some adhoc profiling booting Linux VMs, it's observed that ahci_irq_lower() can be a hot path (10000+ triggers until login prompt appears). Even though the parent device never changes, this method re-determines whether the parent device is a PCI device or not using the rather expensive object_dynamic_cast() function. Avoid this overhead by pushing the interrupt handling to the parent device, essentially turning AHCIState into an "IP block". Note that this change also frees AHCIState from the PCI dependency which wasn't reflected in Kconfig. Reported-by: Peter Xu <peterx@redhat.com> Inspired-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20241212110926.23548-2-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-12-14hw/nvram/fw_cfg: Remove fw_cfg_add_extra_pci_roots()Philippe Mathieu-Daudé1-9/+0
Now that all uses of fw_cfg_add_extra_pci_roots() have been converted to the newer pci_bus_add_fw_cfg_extra_pci_roots(), we can remove that bogus method. hw/nvram/fw_cfg must stay generic. Device specific entries have to be implemented using TYPE_FW_CFG_DATA_GENERATOR_INTERFACE. This mostly reverts commit 0abd38885ac0fcdb08653922f339849cad387961 ("fw_cfg: Refactor extra pci roots addition"). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20241206181352.6836-7-philmd@linaro.org>
2024-12-14hw/pci: Add pci_bus_add_fw_cfg_extra_pci_roots() helperPhilippe Mathieu-Daudé1-0/+3
pci_bus_add_fw_cfg_extra_pci_roots() calls the fw_cfg API with PCI bus specific arguments. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20241206181352.6836-5-philmd@linaro.org>
2024-12-14hw/nvram/fw_cfg: Skip FW_CFG_DATA_GENERATOR when no data to generatePhilippe Mathieu-Daudé1-5/+8
Allow the FW_CFG_DATA_GENERATOR interface get_data() handler to return NULL when there is nothing to generate. In that case fw_cfg_add_file_from_generator() will not add any item and return %true. Reported-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20241213133352.10915-4-philmd@linaro.org>
2024-12-13hw/nvram/fw_cfg: Pass QOM parent to fw_cfg_add_file_from_generator()Philippe Mathieu-Daudé1-4/+6
Currently fw_cfg_add_file_from_generator() is restricted to command line created objects which reside in the '/objects' QOM container. In order to extend to other types of containers, pass the QOM parent by argument. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20241206181352.6836-3-philmd@linaro.org>
2024-12-13hw/nvram/fw_cfg: Rename fw_cfg_add_[file]_from_generator()Philippe Mathieu-Daudé1-3/+3
fw_cfg_add_from_generator() is adding a 'file' entry, so rename as fw_cfg_add_file_from_generator() for clarity. Besides, we might introduce generators for other entry types. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20241206181352.6836-2-philmd@linaro.org>
2024-12-13hw/core/eif: Use stateful qcrypto apisDorjoy Chowdhury1-8/+8
We were storing the pointers to buffers in a GList due to lack of stateful crypto apis and instead doing the final hash computation at the end after we had all the necessary buffers. Now that we have the stateful qcrypto apis available, we can instead update the hashes inline in the read_eif_* functions which makes the code much simpler. Signed-off-by: Dorjoy Chowdhury <dorjoychy111@gmail.com> Reviewed-by: Alexander Graf <graf@amazon.com> Message-ID: <20241109123039.24180-1-dorjoychy111@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-12-12Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi2-10/+2
* rust: better integration with clippy, rustfmt and rustdoc * rust: interior mutability types * rust: add a bit operations module * rust: first part of QOM rework * kvm: remove unnecessary #ifdef * clock: small cleanups, improve handling of Clock lifetimes # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmdZqFkUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroOzRwf/SYUD+CJCn2x7kUH/JG893jwN1WbJ # meGZ0PQDUpOZJFWg6T4g0MuW4O+Wevy2pF4SfGojgqaYxKBbTQVkeliDEMyNUxpr # vSKXego0K3pkX3cRDXNVTaXFbsHsMt/3pfzMQM6ocF9qbL+Emvx7Og6WdAcyJ4hc # lA17EHlnrWKUSnqN/Ow/pZXsa4ijCklXFFh4barfbdGVhMQc2QekUU45GsP2AvGT # NkXTQC05HqxBaAIDeSxbprDSzNihyT71dAooVoxqKboprPu5uoUSJwgaD8rADPr4 # EOfsz61V4mji+DWDcIzTtYoAdY41vVXI9lvCKOcCFkimA29xO0W6P7mG2w== # =JSh5 # -----END PGP SIGNATURE----- # gpg: Signature made Wed 11 Dec 2024 09:57:29 EST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (49 commits) rust: qom: change the parent type to an associated type rust: qom: split ObjectType from ObjectImpl trait rust: qom: move bridge for TypeInfo functions out of pl011 rust: qdev: move bridge for realize and reset functions out of pl011 rust: qdev: move device_class_init! body to generic function, ClassInitImpl implementation to macro rust: qom: move ClassInitImpl to the instance side rust: qom: convert type_info! macro to an associated const rust: qom: rename Class trait to ClassInitImpl rust: qom: add default definitions for ObjectImpl rust: add a bit operation module rust: add bindings for interrupt sources rust: define prelude rust: cell: add BQL-enforcing RefCell variant rust: cell: add BQL-enforcing Cell variant bql: check that the BQL is not dropped within marked sections qom/object: Remove type_register() script/codeconverter/qom_type_info: Deprecate MakeTypeRegisterStatic and MakeTypeRegisterNotStatic ui: Replace type_register() with type_register_static() target/xtensa: Replace type_register() with type_register_static() target/sparc: Replace type_register() with type_register_static() ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-12-12Merge tag 'pull-target-arm-20241211' of ↵Stefan Hajnoczi3-5/+47
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * hw/net/lan9118: Extract PHY model, reuse with imx_fec, fix bugs * fpu: Make muladd NaN handling runtime-selected, not compile-time * fpu: Make default NaN pattern runtime-selected, not compile-time * fpu: Minor NaN-related cleanups * MAINTAINERS: email address updates # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmdZu14ZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3mgiD/98Q+m7/t54FdCd2bx1cr2k # dw+7DYhp+60Vo3OjlGtKWwPD67oN8e0jhOoArmJNW0Fmkcsvfvd4wv6kCf8zftLm # 0/lPO687mvFNCAprTch+z2pGB7aS0HdIr126ytsyg5PlHtldd+OBA+yUUYafR3zo # BECRSWZmMFxfl9uckJzntdntghTX5pnJDSGBYE9NEyRfo0Ntj1HvhaHSQJkqpf5B # QwE8R965CXc4i34PqlOCju47AXwJc3x36ftdiNmpPvMS4odG9yb/OmhHSgVZlThb # 1x0HEX69KF5FQbtVNDMmFyYehDzqYFpqOSa1IKtaNLmDSZJ5P8fWw4eBdMdr/QyD # QKssgHAO6Z13MLppK4B1PFtSVlsLYUURYddYUFz4RUNOxrS/pzAIT0KhClYFytQo # x9xid4fng1PY9doYEM3v4vEQCU6S+2aj2gU4EOwdB8GmMhtjSl8YlcEs7cysqkoQ # gbGX97i6Eh616q9VsRzUwcY6u4XP/lssn6I98k4AEqgRpyFCMTLyFodV89d6J4EJ # IJKsJf10gctpe1JdMgtDxuleKOZc+O5nOMJLKYwc9siakCBZsH7zmgS6m8QVoUSD # 7R+4OtbaQwM0+GPbc0AhAlDtq3Q1QAtCYa94iICUixC4NjzfdC9B9yCz1XnA7sfS # jPHU8INw6rz3psEnlFQdhA== # =+ELh # -----END PGP SIGNATURE----- # gpg: Signature made Wed 11 Dec 2024 11:18:38 EST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20241211' of https://git.linaro.org/people/pmaydell/qemu-arm: (72 commits) MAINTAINERS: Add correct email address for Vikram Garhwal MAINTAINERS: update email address for Leif Lindholm softfloat: Replace WHICH with RET in parts_pick_nan softfloat: Sink frac_cmp in parts_pick_nan until needed softfloat: Share code between parts_pick_nan cases softfloat: Inline pickNaN softfloat: Use parts_pick_nan in propagateFloatx80NaN softfloat: Move propagateFloatx80NaN to softfloat.c softfloat: Pad array size in pick_nan_muladd softfloat: Remove which from parts_pick_nan_muladd softfloat: Use goto for default nan case in pick_nan_muladd softfloat: Inline pickNaNMulAdd fpu: Remove default handling for dnan_pattern target/tricore: Set default NaN pattern explicitly target/riscv: Set default NaN pattern explicitly target/hexagon: Set default NaN pattern explicitly target/xtensa: Set default NaN pattern explicitly target/sparc: Set default NaN pattern explicitly target/s390x: Set default NaN pattern explicitly target/rx: Set default NaN pattern explicitly ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-12-12Merge tag 'pull-request-2024-12-11' of https://gitlab.com/thuth/qemu into ↵Stefan Hajnoczi2-1/+9
staging * Add compat machines for QEMU 10.0 * Add s390x CPU model for the gen17 mainframe * Convert some more avocado tests to the new functional framework * Some minor clean-ups for functional tests # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmdZUu0RHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbVpzBAAo/xldyDvEBkQiHpw7YF5x6dipSdQmgbL # 02Qq1p2A7LxGK7uv6HBtOwhxk2eB0F+o8ZNt79u6QJmrI7Anme40B6GRXKHpm+Nn # 2zn6xzBKnKJSjI/mr3zNqQwCb+q68hL+0N9oNSlbl42uElnMNMr1elkW7W+YT70d # w+P5UzV2AuvjC6ML1R6ULwJHdeoklAk87g7l3Ns5z8CPFCV3yMOzGHqgpYQdYl+U # Cx0CT/xqkfoyustkbPSCUGDzZbLQLMHcCgGX9DVLUmP8I6U1MeZC3HIxYdI4ofX/ # ApFQ4ThMV5f0A6hnn2TRrP+74He6wjYkB3RUjXtchVizWm1FZhNNa//cWvoEmCFU # ufwuAFNvTodli0/47GEmwu8t/jqXJ1SeC50VAPyzxpedJwkgaMAZiYAlDO/oxIY1 # BCNR5bDjf4pAzguHG4FnPxaOcb5UT+V+sukQMvxa03TGrTp2/U9sanCVVdGPOovI # sf/nXsK6jYe1mvinLF9wTyAjjkXqboqfgRabQi2DRgP/FMKseGapy4fOOXzj5Flv # 5FSdyzm4/3fnb2fl1cWSNqPCLwAtmPWx0weu7PBbhP7AwNEXbpJcHmjtJwxL5Slx # c+qazS6lbeBphPlToEqhibOZAxMM6QYvFxhL8Ut36vyEBbO/LAjy9+od9/jb8QCd # ijtWjauVpHc= # =BG+s # -----END PGP SIGNATURE----- # gpg: Signature made Wed 11 Dec 2024 03:53:01 EST # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2024-12-11' of https://gitlab.com/thuth/qemu: (26 commits) tests/functional: remove pointless with statement tests/functional: remove unused system imports tests/functional: Convert the cubieboard avocado tests tests/functional: Convert the smdkc210 avocado test tests/functional: Convert the emcraft_sf2 avocado test tests/functional: Convert the xlnx_versal_virt avocado test MAINTAINERS: Cover the tests/functional/test_sh4eb_r2d.py file tests/functional: Bump the timeout of the sh4_tuxrun test s390x/cpumodel: gen17 model s390x/cpumodel: Add PLO-extension facility s390x/cpumodel: correct PLO feature wording s390x/cpumodel: Add Sequential-Instruction-Fetching facility s390x/cpumodel: add Ineffective-nonconstrained-transaction facility s390x/cpumodel: add Vector-Packed-Decimal-Enhancement facility 3 s390x/cpumodel: add Miscellaneous-Instruction-Extensions Facility 4 s390x/cpumodel: add Vector Enhancements facility 3 s390x/cpumodel: add Concurrent-functions facility support linux-headers: Update to Linux 6.13-rc1 s390x/cpumodel: Add ptff Query Time-Stamp Event (QTSE) support s390x/cpumodel: add msa13 subfunctions ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-12-11hw/net/lan9118_phy: Reuse MII constantsBernhard Beschow1-0/+6
Prefer named constants over magic values for better readability. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Tested-by: Guenter Roeck <linux@roeck-us.net> Message-id: 20241102125724.532843-5-shentey@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-11hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementationsBernhard Beschow1-5/+4
imx_fec models the same PHY as lan9118_phy. The code is almost the same with imx_fec having more logging and tracing. Merge these improvements into lan9118_phy and reuse in imx_fec to fix the code duplication. Some migration state how resides in the new device model which breaks migration compatibility for the following machines: * imx25-pdk * sabrelite * mcimx7d-sabre * mcimx6ul-evk Signed-off-by: Bernhard Beschow <shentey@gmail.com> Tested-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20241102125724.532843-3-shentey@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-11hw/net/lan9118: Extract lan9118_phyBernhard Beschow1-0/+37
A very similar implementation of the same device exists in imx_fec. Prepare for a common implementation by extracting a device model into its own files. Some migration state has been moved into the new device model which breaks migration compatibility for the following machines: * smdkc210 * realview-* * vexpress-* * kzm * mps2-* While breaking migration ABI, fix the size of the MII registers to be 16 bit, as defined by IEEE 802.3u. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Tested-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20241102125724.532843-2-shentey@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-11hw: add compat machines for 10.0Cornelia Huck2-0/+6
Add 10.0 machine types for arm/i440fx/m68k/q35/s390x/spapr. Signed-off-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20241126103005.3794748-3-cohuck@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-12-11hw/i386: define _AS_LATEST() macros for machine typesDaniel P. Berrangé1-1/+3
Follow the other architecture targets by adding extra macros for defining a versioned machine type as the latest. This reduces the size of the changes when introducing new machine types at the start of each release cycle. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20240910163041.3764176-1-berrange@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com> Message-ID: <20241126103005.3794748-2-cohuck@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-12-11hw/sd/aspeed_sdhci: Add AST2700 SupportJamin Lin1-0/+1
Introduce a new ast2700 class to support AST2700. Add a new ast2700 SDHCI class init function and set the value of capability register to "0x0000000719f80080". Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/r/20241204084453.610660-5-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2024-12-11hw:sdhci: Introduce a new "capareg" class member to set the different ↵Jamin Lin1-2/+10
Capability Registers Currently, it set the hardcode value of capability registers to all ASPEED SOCs However, the value of capability registers should be different for all ASPEED SOCs. For example: the bit 28 of the Capability Register 1 should be 1 for 64-bits System Bus support for AST2700. Introduce a new "capareg" class member whose data type is uint_64 to set the different Capability Registers to all ASPEED SOCs. The value of Capability Register is "0x0000000001e80080" for AST2400 and AST2500. The value of Capability Register is "0x0000000701f80080" for AST2600. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/r/20241204084453.610660-4-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2024-12-10i386: Replace type_register() with type_register_static()Zhao Liu1-2/+2
Replace type_register() with type_register_static() because type_register() will be deprecated. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Link: https://lore.kernel.org/r/20241029085934.2799066-11-zhao1.liu@intel.com
2024-12-10clock: clear callback on unparentPaolo Bonzini1-8/+0
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-11-28Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Peter Maydell1-2/+0
into staging virtio,pc,pci: bug fixes, new test Some small bug fixes, notably a fix for a regression in cpu hotplug after migration. I also included a new test, just to help make sure we don't regress cxl. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmdHJRIPHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRpTkQIAJYFpFTPRnO8mA6gurfheB7Jt0ywAMrjKWfg # uEkfZXXSQeCS8NBNPoZt7S8AE6xHE2a4b5lNWiS4a4coFmgTjtKPM8YsU01riyRk # EasRxynGua2XGUWGK93r9L27v9zGz/vRC0Lujmw3VAUKGeL7a17KzmxwXLXe+DzS # PgcI/H5hqoCDalT8aF6wOEDaWIHeo4dauDubYavW/+yaPtUvmy9MBkXbIV4iYqT5 # V6geeYIKW/yE/GHxxXOw/RE1FgpiZhebtQP26jPTSk0z/JaV5S0DNYs07joXmbaU # fW5LSLgH3+oDI/GIhvsZ6hP87rVXBdaAogeJqT8SsuChBR55TpY= # =B7KB # -----END PGP SIGNATURE----- # gpg: Signature made Wed 27 Nov 2024 13:56:34 GMT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: vhost: fail device start if iotlb update fails bios-tables-test: Add data for complex numa test (GI, GP etc) bios-tables-test: Add complex SRAT / HMAT test for GI GP bios-tables-test: Allow for new acpihmat-generic-x test data. qapi/qom: Change Since entry for AcpiGenericPortProperties to 9.2 hw/acpi: Fix size of HID in build_append_srat_acpi_device_handle() qapi: fix device-sync-config since-version hw/cxl: Check for zero length features in cmd_features_set_feature() tests/acpi: update expected blobs Revert "hw/acpi: Make CPUs ACPI `presence` conditional during vCPU hot-unplug" Revert "hw/acpi: Update ACPI `_STA` method with QOM vCPU ACPI Hotplug states" qtest: allow ACPI DSDT Table changes vhost_net: fix assertion triggered by batch of host notifiers processing Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-11-27hw/pci: Remove unused pci_irq_pulse() methodPhilippe Mathieu-Daudé1-10/+0
Last use of pci_irq_pulse() was removed 7 years ago in commit 5e9aa92eb1 ("hw/block: Fix pin-based interrupt behaviour of NVMe"). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20241122103418.539-1-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-11-26Revert "hw/acpi: Make CPUs ACPI `presence` conditional during vCPU hot-unplug"Igor Mammedov1-1/+0
This reverts commit 2d6cfbaf174b91dfa9a50065f7494634afb39c23. The patch is supposed to be part of ARM CPU hotplug series and has not value on its own without it. The series however is still in RFC stage and outside of scope 9.2 release. On top of that it introduces not needed callback that pokes directly into CPU state without any need for that. Instead properties and AML generator option should be used to configure static platform depended vCPU presence state. Drop the patch so that corrected version could be posted along with ARM CPU hotplug series and properly reviewed in relevant context. That also helps us to keep history cleaner with new patch being against original code vs a string of fixups on top of current mess. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20241112170258.2996640-4-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2024-11-26Revert "hw/acpi: Update ACPI `_STA` method with QOM vCPU ACPI Hotplug states"Igor Mammedov1-1/+0
This reverts commit bf1ecc8dad6061914730a2a2d57af6b37c3a4f8d which broke cpu hotplug in x86 after migration to older QEMU Fixes: bf1ecc8dad606 (w/acpi: Update ACPI `_STA` method with QOM vCPU ACPI Hotplug states) Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20241112170258.2996640-3-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2024-11-26virtio-net: Add queues before loading themAkihiko Odaki1-0/+2
Call virtio_net_set_multiqueue() to add queues before loading their states. Otherwise the loaded queues will not have handlers and elements in them will not be processed. Cc: qemu-stable@nongnu.org Fixes: 8c49756825da ("virtio-net: Add only one queue pair when realizing") Reported-by: Laurent Vivier <lvivier@redhat.com> Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2024-11-19hw/intc/arm_gicv3: Use bitops.h uint32_t bit array functionsPeter Maydell1-40/+14
Now we have official uint32_t bit array functions in bitops.h, use them instead of the hand-rolled local versions. We retain gic_bmp_replace_bit() because bitops doesn't provide that specific functionality. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20241108135514.4006953-3-peter.maydell@linaro.org
2024-11-18Merge tag 'pull-request-2024-11-18' of https://gitlab.com/thuth/qemu into ↵Peter Maydell2-1/+4
staging * Fixes & doc updates for the new "boot order" s390x bios feature * Provide a "loadparm" property for scsi-hd & scsi-cd devices on s390x (required for the "boot order" feature) * Fix the floating-point multiply-and-add NaN rules on s390x * Raise timeout on cross-accel build jobs to 60m # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmc7ercRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbVjyg//ZuhSDCj+oBSU6vwM7Lwh3CS6GwZvGECU # h60V3tizKypiRNtTJRXHoWcx95brXmoZgI+QQhDEXe3fFLkOEKT6AIlDhrKZRUsd # rpLPr6O8TVKO+rSE7JVJAP3X1tpOOQDxnq83uWBv53b0S+Da0VwDRtI9gcugRMmh # d58P8Q1bV344fQdcrebejstpSUG7RxSA4Plj2uSQx4mSHT7cy/hN+vA34Ha7reE3 # tcN9yfQq3Rmfvt0MV5I9Umd6JXEoDlEAwjSNsWRsCzo69jBZwiMtXSH8LyLtwRTp # C919G/MIRuhvImF74dStLVCr82sNq54YR1NP6CGcmqPH76FOH8Mx3vmx9Cxj9ckA # 6NI6SvIg++bW2O1efG2apz8p5fjbDzYXSAbHnaWTcEu3gPgH4PQ5QXoyKaDymvWV # JIh5/gXEy+twEXgIBsdWQ44A9E06lL/tNfKnqGdXK4ZYF2JIrI+Lq7AKBee7tebP # +72I4PljHLSHQ3GxdkoOeJ8ahu70IBdSz2/VEIwOWK1wIf5C5WFNBerLJyDmkyx8 # xIvIm0vlRLwPcuOC711nlaMaKqTNT+8W4DIqIY6fHs2Jy0psMdgey1uHQxYEj9Kh # fg7CvalK8n3MkGAwTqAvRJIwMFe0a4Ss6c6CaemSaYa38ud/pCNnv+IT+Eqr+mjq # 6y5PZWNrZi0= # =UaDH # -----END PGP SIGNATURE----- # gpg: Signature made Mon 18 Nov 2024 17:34:47 GMT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2024-11-18' of https://gitlab.com/thuth/qemu: .gitlab-ci.d: Raise timeout on cross-accel build jobs to 60m pc-bios: Update the s390 bios images with the recent fixes pc-bios/s390-ccw: Re-initialize receive queue index before each boot attempt pc-bios/s390x: Initialize machine loadparm before probing IPL devices pc-bios/s390x: Initialize cdrom type to false for each IPL device hw: Add "loadparm" property to scsi disk devices for booting on s390x hw/s390x: Restrict "loadparm" property to devices that can be used for booting docs/system/bootindex: Make it clear that s390x can also boot from virtio-net docs/system/s390x/bootdevices: Update loadparm documentation tests/tcg/s390x: Add the floating-point multiply-and-add test target/s390x: Fix the floating-point multiply-and-add NaN rules hw/usb: Use __attribute__((packed)) vs __packed Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-11-18hw: Add "loadparm" property to scsi disk devices for booting on s390xThomas Huth1-0/+3
While adding the new flexible boot order feature on s390x recently, we missed to add the "loadparm" property to the scsi-hd and scsi-cd devices. This property is required on s390x to pass the information to the boot loader about which kernel should be started or whether the boot menu should be shown. But even more serious: The missing property is now causing trouble with the corresponding libvirt patches that assume that the "loadparm" property is either settable for all bootable devices (when the "boot order" feature is implemented in QEMU), or none (meaning the behaviour of older QEMUs that only allowed one "loadparm" at the machine level). To fix this broken situation, let's implement the "loadparm" property in for the SCSI devices, too. Message-ID: <20241115141202.1877294-1-thuth@redhat.com> Acked-by: Eric Farman <farman@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-11-18hw/net/virtio-net.c: Don't assume IP length field is alignedPeter Maydell1-1/+1
In virtio-net.c we assume that the IP length field in the packet is aligned, and we copy its address into a uint16_t* in the VirtioNetRscUnit struct which we then dereference later. This isn't a safe assumption; it will also result in compilation failures if we mark the ip_header struct as QEMU_PACKED because the compiler will not let you take the address of an unaligned struct field. Make the ip_plen field in VirtioNetRscUnit a void*, and make all the places where we read or write through that pointer instead use some new accessor functions read_unit_ip_len() and write_unit_ip_len() which account for the pointer being potentially unaligned and also do the network-byte-order conversion we were previously using htons() to perform. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20241114141619.806652-2-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-18hw/misc/mos6522: Fix bad class definition of the MOS6522 deviceThomas Huth1-1/+1
When compiling QEMU with --enable-cfi, the "q800" m68k machine currently crashes very early, when the q800_machine_init() function tries to wire the interrupts of the "via1" device. This happens because TYPE_MOS6522_Q800_VIA1 is supposed to be a proper SysBus device, but its parent (TYPE_MOS6522) has a mistake in its class definition where it is only derived from DeviceClass, and not from SysBusDeviceClass, so we end up in funny memory access issues here. Using the right class hierarchy for the MOS6522 device fixes the problem. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2675 Signed-off-by: Thomas Huth <thuth@redhat.com> Fixes: 51f233ec92 ("misc: introduce new mos6522 VIA device") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-ID: <20241114104653.963812-1-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-18hw/display: check frame buffer can hold blobAlex Bennée1-1/+1
Coverity reports (CID 1564769, 1564770) that we potentially overflow by doing some 32x32 multiplies for something that ends up in a 64 bit value. Fix this by first using stride for all lines and casting input to uint64_t to ensure a 64 bit multiply is used. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Dmitry Osipenko <dmitry.osipenko@collabora.com> Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Message-ID: <20241111230040.68470-3-alex.bennee@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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