diff options
| author | Tomasz Jeznach <tjeznach@rivosinc.com> | 2024-11-06 10:34:03 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-12-20 11:19:16 +1000 |
| commit | 5b128435dcf1e6545b544e3e402470ecf5b45ac7 (patch) | |
| tree | 9948b4210997873b353c1632f1abd3046056327f /include/hw | |
| parent | d13346d105c396e0d95851b58f52cac43ad55952 (diff) | |
| download | qemu-5b128435dcf1e6545b544e3e402470ecf5b45ac7.zip qemu-5b128435dcf1e6545b544e3e402470ecf5b45ac7.tar.gz qemu-5b128435dcf1e6545b544e3e402470ecf5b45ac7.tar.bz2 | |
hw/riscv: add riscv-iommu-sys platform device
This device models the RISC-V IOMMU as a sysbus device. The same design
decisions taken in the riscv-iommu-pci device were kept, namely the
existence of 4 vectors are available for each interrupt cause.
The WSIs are emitted using the input of the s->notify() callback as a
index to an IRQ list. The IRQ list starts at 'base_irq' and goes until
base_irq + 3. This means that boards must have 4 contiguous IRQ lines
available, starting from 'base_irq'.
Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241106133407.604587-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include/hw')
| -rw-r--r-- | include/hw/riscv/iommu.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/hw/riscv/iommu.h b/include/hw/riscv/iommu.h index 80769a1..fc20808 100644 --- a/include/hw/riscv/iommu.h +++ b/include/hw/riscv/iommu.h @@ -33,4 +33,8 @@ typedef struct RISCVIOMMUSpace RISCVIOMMUSpace; OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStatePci, RISCV_IOMMU_PCI) typedef struct RISCVIOMMUStatePci RISCVIOMMUStatePci; +#define TYPE_RISCV_IOMMU_SYS "riscv-iommu-device" +OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStateSys, RISCV_IOMMU_SYS) +typedef struct RISCVIOMMUStateSys RISCVIOMMUStateSys; + #endif |