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2024-02-08Merge tag 'for-upstream' of https://repo.or.cz/qemu/kevin into stagingPeter Maydell2-5/+2
Block layer patches - Allow concurrent BB context changes - virtio: Re-enable notifications after drain - virtio-blk: Fix missing use of irqfd - scsi: Don't ignore most usb-storage properties - blkio: Respect memory-alignment for bounce buffer allocations - iotests tmpdir fixes - virtio-blk: Code cleanups # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEE3D3rFZqa+V09dFb+fwmycsiPL9YFAmXEkwgRHGt3b2xmQHJl # ZGhhdC5jb20ACgkQfwmycsiPL9Y3jA//TmSBVqHljauyImYOgCt8qCXACttV0xhQ # Q5ldUNx/JmIFMoUR7OlpVAL2MtvdwE0jjY+sDlEmWtz4IFJcCsCTUCHZZb8blreb # +mnMkqrQ6Nb3tPR2jeIknrXqNy1ffyjZItktjWXVcl6jaHB8YabHHqszs9DIaf4n # lcKovBKxula8ckMgvm48wCwTtS7VEPeuC5FrOqUqTtuhg+QKp5ZVoyVFHtf6GKTD # iuXzCd4yxu4fDKAthJJj4N1bQaOmCKU7K9N/665wj9P2TyfmwlBAfNwNAlYbdX1E # Sv7eSioQs2+oUxmfD/PUsF7wTYtDCrSAUFn1kP/XdRyXPJR3dHGiBKV9w9CaWNrU # y8rqOhxVcuoBLRljTF32BK4HniAREjRngtpT2FnQQIyedZrXIwyTAWjs+LW12T6O # NMiU603Nl9ZYhO1et2+qspsVpNIfEpQWpK+OCon6E+ggj1ea+pfqU30VPx4JU05I # VLiydluIbehSkRlTHgFcTgApmx843OGW7CvWfRyen86Cexgx3DEjJUQ4/bYqaCha # yLIi91rToSDmtlzJrg9eYiMs5Y6vz+ORvvX5im1RlbUUb7Kx/LaA4BU/uArEbBt8 # xXm/grO4hFUGqtLgd2LIjWaHSsLoW4jKeEiExFUUfvH5DG9Zl5HmzFwu+DYxX+im # MJLLetDJAWI= # =8tc0 # -----END PGP SIGNATURE----- # gpg: Signature made Thu 08 Feb 2024 08:38:32 GMT # gpg: using RSA key DC3DEB159A9AF95D3D7456FE7F09B272C88F2FD6 # gpg: issuer "kwolf@redhat.com" # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" [full] # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * tag 'for-upstream' of https://repo.or.cz/qemu/kevin: virtio-blk: avoid using ioeventfd state in irqfd conditional virtio-blk: Use ioeventfd_attach in start_ioeventfd virtio: Re-enable notifications after drain virtio-scsi: Attach event vq notifier with no_poll blkio: Respect memory-alignment for bounce buffer allocations scsi: Don't ignore most usb-storage properties virtio-blk: do not use C99 mixed declarations iotests: give tempdir an identifying name iotests: fix leak of tmpdir in dry-run mode scsi: Await request purging block-backend: Allow concurrent context changes monitor: use aio_co_reschedule_self() virtio-blk: declare VirtIOBlock::rq with a type virtio-blk: add vq_rq[] bounds check in virtio_blk_dma_restart_cb() virtio-blk: clarify that there is at least 1 virtqueue virtio-blk: enforce iothread-vq-mapping validation Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-07scsi: Don't ignore most usb-storage propertiesKevin Wolf1-4/+1
usb-storage is for the most part just a wrapper around an internally created scsi-disk device. It uses DEFINE_BLOCK_PROPERTIES() to offer all of the usual block device properties to the user, but then only forwards a few select properties to the internal device while the rest is silently ignored. This changes scsi_bus_legacy_add_drive() to accept a whole BlockConf instead of some individual values inside of it so that usb-storage can now pass the whole configuration to the internal scsi-disk. This enables the remaining block device properties, e.g. logical/physical_block_size or discard_granularity. Buglink: https://issues.redhat.com/browse/RHEL-22375 Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-ID: <20240131130607.24117-1-kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2024-02-07virtio-blk: declare VirtIOBlock::rq with a typeStefan Hajnoczi1-1/+1
The VirtIOBlock::rq field has had the type void * since its introduction in commit 869a5c6df19a ("Stop VM on error in virtio-blk. (Gleb Natapov)"). Perhaps this was done to avoid the forward declaration of VirtIOBlockReq. Hanna Czenczek <hreitz@redhat.com> pointed out the missing type. Specify the actual type because there is no need to use void * here. Suggested-by: Hanna Czenczek <hreitz@redhat.com> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Hanna Czenczek <hreitz@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-ID: <20240206190610.107963-5-stefanha@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2024-02-06oslib-posix: initialize backend memory objects in parallelMark Kanda1-0/+5
QEMU initializes preallocated backend memory as the objects are parsed from the command line. This is not optimal in some cases (e.g. memory spanning multiple NUMA nodes) because the memory objects are initialized in series. Allow the initialization to occur in parallel (asynchronously). In order to ensure optimal thread placement, asynchronous initialization requires prealloc context threads to be in use. Signed-off-by: Mark Kanda <mark.kanda@oracle.com> Message-ID: <20240131165327.3154970-2-mark.kanda@oracle.com> Tested-by: Mario Casquero <mcasquer@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com>
2024-02-03Merge tag 'pull-tcg-20240202-2' of https://gitlab.com/rth7680/qemu into stagingPeter Maydell1-0/+3
tests/tcg: Fix multiarch/gdbstub/prot-none.py hw/core: Convert cpu_mmu_index to a CPUClass hook tcg/loongarch64: Set vector registers call clobbered target/sparc: floating-point cleanup linux-user/aarch64: Add padding before __kernel_rt_sigreturn # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmW95WkdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/p+Qf/eVmh5q0pZqcur7ft # 8FO0wlIz55OfhaA9MIpH7LEIHRKY37Ybebw2K6SPnx4FmPhLkaj4KXPPjT2nzdXw # J2nQM+TOyxOd18GG8P80qFQ1a72dj8VSIRVAl9T46KuPXS5B7luArImfBlUk/GwV # Qr/XkOPwVTp05E/ccMJ8PMlcVZw9osHVLqsaFVbsUv/FylTmstzA9c5Gw7/FTfkG # T2rk+7go+F4IXs/9uQuuFMOpQOZngXE621hnro+qle7j9oarEUVJloAgVn06o59O # fUjuoKO0aMCr2iQqNJTH7Dnqp5OIzzxUoXiNTOj0EimwWfAcUKthoFO2LGcy1/ew # wWNR/Q== # =e3J3 # -----END PGP SIGNATURE----- # gpg: Signature made Sat 03 Feb 2024 07:04:09 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20240202-2' of https://gitlab.com/rth7680/qemu: (58 commits) linux-user/aarch64: Add padding before __kernel_rt_sigreturn target/sparc: Remove FSR_FTT_NMASK, FSR_FTT_CEXC_NMASK target/sparc: Split fcc out of env->fsr target/sparc: Remove cpu_fsr target/sparc: Split cexc and ftt from env->fsr target/sparc: Merge check_ieee_exceptions with FPop helpers target/sparc: Clear cexc and ftt in do_check_ieee_exceptions target/sparc: Split ver from env->fsr target/sparc: Introduce cpu_get_fsr, cpu_put_fsr target/sparc: Remove qt0, qt1 temporaries target/sparc: Use i128 for Fdmulq target/sparc: Use i128 for FdTOq, FxTOq target/sparc: Use i128 for FsTOq, FiTOq target/sparc: Use i128 for FCMPq, FCMPEq target/sparc: Use i128 for FqTOd, FqTOx target/sparc: Use i128 for FqTOs, FqTOi target/sparc: Use i128 for FADDq, FSUBq, FMULq, FDIVq target/sparc: Use i128 for FSQRTq target/sparc: Inline FNEG, FABS target/sparc: Introduce gen_{load,store}_fpr_Q ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-03include/hw/core: Add mmu_index to CPUClassRichard Henderson1-0/+3
To be used after all targets have populated the hook. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-02Merge tag 'pull-target-arm-20240202' of ↵Peter Maydell6-6/+428
https://git.linaro.org/people/pmaydell/qemu-arm into staging target/arm: fix exception syndrome for AArch32 bkpt insn pci, vmbus, adb, s390x/css-bridge: Switch buses to 3-phase reset system/vl.c: Fix handling of '-serial none -serial something' target/arm: Add ID_AA64ZFR0_EL1.B16B16 to the exposed-to-userspace set tests/qtest/xlnx-versal-trng-test.c: Drop use of variable length array target/arm: Reinstate "vfp" property on AArch32 CPUs doc/sphinx/hxtool.py: add optional label argument to SRST directive hw/arm: Check for CPU types in machine_run_board_init() for various boards pci-host: designware: Limit value range of iATU viewport register hw/arm: Convert some DPRINTF macros to trace events and guest errors hw/arm: NPCM7XX SoC: Add GMAC ethernet controller devices hw/arm: Implement BCM2835 SPI Controller # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmW9C84ZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3qS6D/wM0/JGEYfaadpuMEOAx4PG # AnfScbPqVhx9J31P2Ks3VrB5F108aq/SaL2BmCb3BLF/ECChlhBXIjd7ukdHstts # F1TvqtvLGDZQz6wSVUeB0YOvAjGa3vIskn+Xvk9e6Ne6PcXgVnxAof/cPsXUiYNy # 6DJjNiLJ/a9Xgq9rjFO6vzW3AL95U6/FmD2F0pOotWXERhNhoyYVV6RtyeqKlDQP # yFVk5h601YURk9PeNZn9zpOpZqjAM7PxyF3X50N3Sv+G0uoKSr6b+c3/fDJbJo3+ # 0LXomEa8hdheQxm1dLY5OD0JX3bvYxwH41bDg9B0iEdjxUdXt6LfXI9Nvw9BAwix # 8AcGJJUaL4XU4uPfHBpRJApM15+MRb0hqfv4ZcGk8e67IIqVeDbKL2clTQGoHSg1 # KaB0POhtFx//M/uBOyk/FR2gb2eBNU8GuoCgxdDwh0K5ylcaK1YPiX4Tcglu4iS0 # Frvazphb2pO1BK6JiJwN2/9ezzDkDJqTKoSqdc4g3ETVOGnxr+tXwcds3t2iK3g2 # y+pgijDOAT3bJO5kYeGvhoEJPKqXwJ3UQ8zTJsU2XSYwBjIyv5V3oOn6elwYJaWq # yUDTC3QEK61KfnQnfTyLfdGWX1aVzHnYLWmQdO+3cczuQU0s0MP246Z1GAgDtgvD # jGjDBz6mryWvP2H0xSmERQ== # =azdP # -----END PGP SIGNATURE----- # gpg: Signature made Fri 02 Feb 2024 15:35:42 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20240202' of https://git.linaro.org/people/pmaydell/qemu-arm: (36 commits) hw/arm: Connect SPI Controller to BCM2835 hw/ssi: Implement BCM2835 SPI Controller tests/qtest: Adding PCS Module test to GMAC Qtest hw/net: GMAC Tx Implementation hw/net: GMAC Rx Implementation tests/qtest: Creating qtest for GMAC Module hw/arm: Add GMAC devices to NPCM7XX SoC hw/net: Add NPCMXXX GMAC device hw/xen: convert stderr prints to error/warn reports hw/xen/xen-hvm-common.c: convert DPRINTF to tracepoints hw/xen/xen-mapcache.c: convert DPRINTF to tracepoints hw/arm/xen_arm.c: convert DPRINTF to trace events and error/warn reports hw/arm/z2: convert DPRINTF to trace events and guest errors hw/arm/strongarm.c: convert DPRINTF to trace events and guest errors pci-host: designware: Limit value range of iATU viewport register hw/arm/zynq: Check for CPU types in machine_run_board_init() hw/arm/vexpress: Check for CPU types in machine_run_board_init() hw/arm/npcm7xx_boards: Simplify setting MachineClass::valid_cpu_types[] hw/arm/musca: Simplify setting MachineClass::valid_cpu_types[] hw/arm/msf2: Simplify setting MachineClass::valid_cpu_types[] ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-02hw/pci: remove pci_nic_init_nofail()David Woodhouse1-3/+0
This function is no longer used, as all its callers have been converted to use pci_init_nic_devices() instead. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
2024-02-02hw/net/lasi_i82596: use qemu_create_nic_device()David Woodhouse1-2/+2
Create the device only if there is a corresponding NIC config for it. Remove the explicit check on nd_table[0].used from hw/hppa/machine.c which (since commit d8a3220005d7) tries to do the same thing. The lasi_82596 support has been disabled since it was first introduced, since enable_lasi_lan() has always been zero. This allows the user to enable it by explicitly requesting a NIC model 'lasi_82596' or just using the alias 'lasi'. Otherwise, it defaults to a PCI NIC as before. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
2024-02-02hw/net/etraxfs-eth: use qemu_configure_nic_device()David Woodhouse1-1/+1
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
2024-02-02hw/net/lan9118: use qemu_configure_nic_device()David Woodhouse1-1/+1
Some callers instantiate the device unconditionally, others will do so only if there is a NICInfo to go with it. This appears to be fairly random, but preseve the existing behaviour for now. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
2024-02-02hw/net/smc91c111: use qemu_configure_nic_device()David Woodhouse1-1/+1
Some callers instantiate the device unconditionally, others will do so only if there is a NICInfo to go with it. This appears to be fairly random, but preserve the existing behaviour of each caller for now. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com>
2024-02-02hw/xen: use qemu_create_nic_bus_devices() to instantiate Xen NICsDavid Woodhouse3-5/+2
When instantiating XenBus itself, for each NIC which is configured with either the model unspecified, or set to to "xen" or "xen-net-device", create a corresponding xen-net-device for it. Now we can revert the previous more hackish version which relied on the platform code explicitly registering the NICs on its own XenBus, having returned the BusState* from xen_bus_init() itself. This also fixes the setup for Xen PV guests, which was previously broken in various ways and never actually managed to peer with the netdev. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Paul Durrant <paul@xen.org>
2024-02-02hw/i386/pc: use qemu_get_nic_info() and pci_init_nic_devices()David Woodhouse1-2/+0
Eliminate direct access to nd_table[] and nb_nics by processing the the Xen and ISA NICs first and then calling pci_init_nic_devices() for the rest. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Paul Durrant <paul@xen.org>
2024-02-02hw/pci: add pci_init_nic_devices(), pci_init_nic_in_slot()David Woodhouse1-1/+3
The loop over nd_table[] to add PCI NICs is repeated in quite a few places. Add a helper function to do it. Some platforms also try to instantiate a specific model in a specific slot, to match the real hardware. Add pci_init_nic_in_slot() for that purpose. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Paul Durrant <paul@xen.org>
2024-02-02hw/arm: Connect SPI Controller to BCM2835Rayhan Faizel1-1/+2
This patch will allow the SPI controller to be accessible from BCM2835 based boards as SPI0. SPI driver is usually disabled by default and config.txt does not work. Instead, dtmerge can be used to apply spi=on on a bcm2835 dtb file. Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com> Message-id: 20240129221807.2983148-3-rayhan.faizel@gmail.com [PMM: indent tweak] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-02hw/ssi: Implement BCM2835 SPI ControllerRayhan Faizel1-0/+81
This patch adds the SPI controller for the BCM2835. Polling and interrupt modes of transfer are supported. DMA and LoSSI modes are currently unimplemented. Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com> Message-id: 20240129221807.2983148-2-rayhan.faizel@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-02hw/arm: Add GMAC devices to NPCM7XX SoCHao Wu1-0/+2
Change-Id: Id8a3461fb5042adc4c3fd6f4fbd1ca0d33e22565 Signed-off-by: Hao Wu <wuhaotsh@google.com> Signed-off-by: Nabih Estefan <nabihestefan@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Message-id: 20240131002800.989285-3-nabihestefan@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-02hw/net: Add NPCMXXX GMAC deviceHao Wu1-0/+343
This patch implements the basic registers of GMAC device and sets registers for networking functionalities. Squashed IRQ Implementation patch into this one for compliation. Tested: The following message shows up with the change: Broadcom BCM54612E stmmac-0:00: attached PHY driver [Broadcom BCM54612E] (mii_bus:phy_addr=stmmac-0:00, irq=POLL) stmmaceth f0802000.eth eth0: Link is Up - 1Gbps/Full - flow control rx/tx Change-Id: If71c6d486b95edcccba109ba454870714d7e0940 Signed-off-by: Hao Wu <wuhaotsh@google.com> Signed-off-by: Nabih Estefan Diaz <nabihestefan@google.com> Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Message-id: 20240131002800.989285-2-nabihestefan@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-02hw/arm/msf2: Simplify setting MachineClass::valid_cpu_types[]Philippe Mathieu-Daudé1-3/+0
The M2Sxxx SoC family can only be used with Cortex-M3. Propagating the CPU type from the board level is pointless. Hard-code the CPU type at the SoC level. Remove the now ignored MachineClass::default_cpu_type field. Use the common code introduced in commit c9cf636d48 ("machine: Add a valid_cpu_types property") to check for valid CPU type at the board level. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240129151828.59544-6-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-02hw/core: Remove transitional infrastructure from BusClassPeter Maydell1-2/+0
BusClass currently has transitional infrastructure to support subclasses which implement the legacy BusClass::reset method rather than the Resettable interface. We have now removed all the users of BusClass::reset in the tree, so we can remove the transitional infrastructure. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Cédric Le Goater <clg@redhat.com> Acked-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com> Tested-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-id: 20240119163512.3810301-6-peter.maydell@linaro.org
2024-02-01Merge tag 'pull-aspeed-20240201' of https://github.com/legoater/qemu into ↵Peter Maydell6-1/+199
staging aspeed queue: * Update of buildroot images to 2023.11 (6.6.3 kernel) * Check of the valid CPU type supported by aspeed machines * Simplified models for the IBM's FSI bus and the Aspeed controller bridge # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmW7Sa8ACgkQUaNDx8/7 # 7KG7mw/8DbMJY6aqgq5YANszzem1ktJphPCNxq081cbczCOUpCNX4aL+0/ANvxxD # lbJQB+SZeIRmuFbxYPhq68rtzB4vG7tsQpns4H33EPKT4vuzF70lq4fgptMiun3q # 1ZJ2LF3jonvQWdhbC17wzAQz0FFb4F7XOxz++UL4okPsgzsYItnd+TWs8q7+erRb # 84UwN+eBTBAl/FiNk679/tBTqAfCVGgQ7dzotr4f3tg5POvrGOrlEjAn0O+dGGDj # wgILmpEBsTsilRB1tz8Kw0j/v/VkHz1DJu45lRAV9CIrN22iKcjMilNGgNDT8kcI # yAlxAw3iN+hVFqDov8wFPjDYd/Qw2oRAPy2Kd14hW9xL8zBOTms1JK5L0PS2+Feo # ZjMJ2cOJq3t4Wt1ZXRhgHfF4ANwP0OZ/y9bHCy3CkBljEeiTQbikHP9gVV4qHXZH # 4Q0HnDZQwAgobw3CmZ8jVx1dQueqy3ycuvkhCyv3S0l/tdbtXDtr5pNNu3dAP/PJ # 3nifLdRImhDvxxO9GKaCdUVLzELzMJl0GrgAsVJPKVnKHA4IiVKmB+XcW9IUbfy/ # 3zA2wHJLrEF+MF6MsuNcEYCCqUvyNLm7rUrXk1wNLXpCJ35bbW5IYy7Ty/8E2GHb # D5Cv/EPNhMBiNA4+HqQlMOTC13Ozv2qwCuWYCh2Ik8mnzaEiyTo= # =0C5S # -----END PGP SIGNATURE----- # gpg: Signature made Thu 01 Feb 2024 07:35:11 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-aspeed-20240201' of https://github.com/legoater/qemu: hw/fsi: Update MAINTAINER list hw/fsi: Added FSI documentation hw/fsi: Added qtest hw/arm: Hook up FSI module in AST2600 hw/fsi: Aspeed APB2OPB & On-chip peripheral bus hw/fsi: Introduce IBM's FSI master hw/fsi: Introduce IBM's cfam hw/fsi: Introduce IBM's fsi-slave model hw/fsi: Introduce IBM's FSI Bus hw/fsi: Introduce IBM's scratchpad device hw/fsi: Introduce IBM's Local bus hw/arm/aspeed: Check for CPU types in machine_run_board_init() hw/arm/aspeed: Introduce aspeed_soc_cpu_type() helper hw/arm/aspeed: Init CPU defaults in a common helper hw/arm/aspeed: Set default CPU count using aspeed_soc_num_cpus() hw/arm/aspeed: Remove dead code tests/avocado/machine_aspeed.py: Update buildroot images to 2023.11 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-01hw/arm: Hook up FSI module in AST2600Ninad Palsule1-0/+4
This patchset introduces IBM's Flexible Service Interface(FSI). Time for some fun with inter-processor buses. FSI allows a service processor access to the internal buses of a host POWER processor to perform configuration or debugging. FSI has long existed in POWER processes and so comes with some baggage, including how it has been integrated into the ASPEED SoC. Working backwards from the POWER processor, the fundamental pieces of interest for the implementation are: 1. The Common FRU Access Macro (CFAM), an address space containing various "engines" that drive accesses on buses internal and external to the POWER chip. Examples include the SBEFIFO and I2C masters. The engines hang off of an internal Local Bus (LBUS) which is described by the CFAM configuration block. 2. The FSI slave: The slave is the terminal point of the FSI bus for FSI symbols addressed to it. Slaves can be cascaded off of one another. The slave's configuration registers appear in address space of the CFAM to which it is attached. 3. The FSI master: A controller in the platform service processor (e.g. BMC) driving CFAM engine accesses into the POWER chip. At the hardware level FSI is a bit-based protocol supporting synchronous and DMA-driven accesses of engines in a CFAM. 4. The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in POWER processors. This now makes an appearance in the ASPEED SoC due to tight integration of the FSI master IP with the OPB, mainly the existence of an MMIO-mapping of the CFAM address straight onto a sub-region of the OPB address space. 5. An APB-to-OPB bridge enabling access to the OPB from the ARM core in the AST2600. Hardware limitations prevent the OPB from being directly mapped into APB, so all accesses are indirect through the bridge. The implementation appears as following in the qemu device tree: (qemu) info qtree bus: main-system-bus type System ... dev: aspeed.apb2opb, id "" gpio-out "sysbus-irq" 1 mmio 000000001e79b000/0000000000001000 bus: opb.1 type opb dev: fsi.master, id "" bus: fsi.bus.1 type fsi.bus dev: cfam.config, id "" dev: cfam, id "" bus: fsi.lbus.1 type lbus dev: scratchpad, id "" address = 0 (0x0) bus: opb.0 type opb dev: fsi.master, id "" bus: fsi.bus.0 type fsi.bus dev: cfam.config, id "" dev: cfam, id "" bus: fsi.lbus.0 type lbus dev: scratchpad, id "" address = 0 (0x0) The LBUS is modelled to maintain the qdev bus hierarchy and to take advantage of the object model to automatically generate the CFAM configuration block. The configuration block presents engines in the order they are attached to the CFAM's LBUS. Engine implementations should subclass the LBusDevice and set the 'config' member of LBusDeviceClass to match the engine's type. CFAM designs offer a lot of flexibility, for instance it is possible for a CFAM to be simultaneously driven from multiple FSI links. The modeling is not so complete; it's assumed that each CFAM is attached to a single FSI slave (as a consequence the CFAM subclasses the FSI slave). As for FSI, its symbols and wire-protocol are not modelled at all. This is not necessary to get FSI off the ground thanks to the mapping of the CFAM address space onto the OPB address space - the models follow this directly and map the CFAM memory region into the OPB's memory region. Future work includes supporting more advanced accesses that drive the FSI master directly rather than indirectly via the CFAM mapping, which will require implementing the FSI state machine and methods for each of the FSI symbols on the slave. Further down the track we can also look at supporting the bitbanged SoftFSI drivers in Linux by extending the FSI slave model to resolve sequences of GPIO IRQs into FSI symbols, and calling the associated symbol method on the slave to map the access onto the CFAM. Testing: Tested by reading cfam config address 0 on rainier machine type. root@p10bmc:~# pdbg -a getcfam 0x0 p0: 0x0 = 0xc0022d15 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Ninad Palsule <ninad@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2024-02-01hw/fsi: Aspeed APB2OPB & On-chip peripheral busNinad Palsule1-0/+46
This is a part of patchset where IBM's Flexible Service Interface is introduced. An APB-to-OPB bridge enabling access to the OPB from the ARM core in the AST2600. Hardware limitations prevent the OPB from being directly mapped into APB, so all accesses are indirect through the bridge. The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in POWER processors. This now makes an appearance in the ASPEED SoC due to tight integration of the FSI master IP with the OPB, mainly the existence of an MMIO-mapping of the CFAM address straight onto a sub-region of the OPB address space. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Ninad Palsule <ninad@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg: - moved FSIMasterState under AspeedAPB2OPBState - modified fsi_opb_fsi_master_address() and fsi_opb_opb2fsi_address() - instroduced fsi_aspeed_apb2opb_init() - reworked fsi_aspeed_apb2opb_realize() - removed FSIMasterState object and fsi_opb_realize() - simplified OPBus - introduced fsi_aspeed_apb2opb_rw to fix endianness issue ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
2024-02-01hw/fsi: Introduce IBM's FSI masterNinad Palsule1-0/+32
This is a part of patchset where IBM's Flexible Service Interface is introduced. This commit models the FSI master. CFAM is hanging out of FSI master which is a bus controller. The FSI master: A controller in the platform service processor (e.g. BMC) driving CFAM engine accesses into the POWER chip. At the hardware level FSI is a bit-based protocol supporting synchronous and DMA-driven accesses of engines in a CFAM. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Ninad Palsule <ninad@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg: - move FSICFAMState object under FSIMasterState - introduced fsi_master_init() - reworked fsi_master_realize() - dropped FSIBus definition ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
2024-02-01hw/fsi: Introduce IBM's cfamNinad Palsule1-0/+34
This is a part of patchset where IBM's Flexible Service Interface is introduced. The Common FRU Access Macro (CFAM), an address space containing various "engines" that drive accesses on busses internal and external to the POWER chip. Examples include the SBEFIFO and I2C masters. The engines hang off of an internal Local Bus (LBUS) which is described by the CFAM configuration block. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Ninad Palsule <ninad@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg: - moved object FSIScratchPad under FSICFAMState - moved FSIScratchPad code under cfam.c - introduced fsi_cfam_instance_init() - reworked fsi_cfam_realize() ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
2024-02-01hw/fsi: Introduce IBM's fsi-slave modelNinad Palsule1-0/+18
This is a part of patchset where IBM's Flexible Service Interface is introduced. The FSI slave: The slave is the terminal point of the FSI bus for FSI symbols addressed to it. Slaves can be cascaded off of one another. The slave's configuration registers appear in address space of the CFAM to which it is attached. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Ninad Palsule <ninad@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2024-02-01hw/fsi: Introduce IBM's FSI BusNinad Palsule1-0/+19
This is a part of patchset where FSI bus is introduced. The FSI bus is a simple bus where FSI master is attached. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Ninad Palsule <ninad@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg: - removed include/hw/fsi/engine-scratchpad.h and hw/fsi/engine-scratchpad.c - dropped FSI_SCRATCHPAD - included FSIBus definition - dropped hw/fsi/trace-events changes ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
2024-02-01hw/fsi: Introduce IBM's scratchpad deviceNinad Palsule1-0/+11
This is a part of patchset where IBM's Flexible Service Interface is introduced. The scratchpad provides a set of non-functional registers. The firmware is free to use them, hardware does not support any special management support. The scratchpad registers can be read or written from LBUS slave. The scratch pad is managed under FSI CFAM state. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Ninad Palsule <ninad@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg: - moved object FSIScratchPad under FSICFAMState - moved FSIScratchPad code under cfam.c ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
2024-02-01hw/fsi: Introduce IBM's Local busNinad Palsule1-0/+32
This is a part of patchset where IBM's Flexible Service Interface is introduced. The LBUS is modelled to maintain mapped memory for the devices. The memory is mapped after CFAM config, peek table and FSI slave registers. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Ninad Palsule <ninad@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg: - removed lbus_add_device() bc unused - removed lbus_create_device() bc used only once - removed "address" property - updated meson.build to build fsi dir - included an empty hw/fsi/trace-events ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
2024-02-01hw/arm/aspeed: Check for CPU types in machine_run_board_init()Philippe Mathieu-Daudé1-1/+2
Aspeed SoCs use a single CPU type (set as AspeedSoCClass::cpu_type). Convert it to a NULL-terminated array (of a single non-NULL element). Set MachineClass::valid_cpu_types[] to use the common machine code to provide hints when the requested CPU is invalid (see commit e702cbc19e ("machine: Improve is_cpu_type_supported()"). Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2024-02-01hw/arm/aspeed: Introduce aspeed_soc_cpu_type() helperPhilippe Mathieu-Daudé1-0/+1
In order to alter AspeedSoCClass::cpu_type in the next commit, introduce the aspeed_soc_cpu_type() helper to retrieve the per-SoC CPU type from AspeedSoCClass. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2024-01-31Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into stagingPeter Maydell8-8/+0
trivial patches for 2024-01-31 # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEe3O61ovnosKJMUsicBtPaxppPlkFAmW6NScPHG1qdEB0bHMu # bXNrLnJ1AAoJEHAbT2saaT5ZdQYH/2fhfhZotH0V2qAcMxlOoHbAE9UhZNRsSYtf # QFP0GXFYFAMm7LHkPUbvKgO7LylKWAOMn/zKZqgj1Vf1EpoKQ2FwLtR/buDz86Ec # pi2OrDPRA7Ay5c3ow3YZZkUOhQTTcR5rNjYctPtt/J4j8ol/z5vre7weJIg2bCJe # zI7vIVg7iFFzbkXY20KHngJ5nDC+aEm7WaGlxAP8kfkvy324Wy9O2k8qu2J5zbLT # HGvh3rwEDvRTYe4CaKFFHWNV0m4092HAr/dJBobugI5VZ6QQpK6Tgy8N+4ZrCHD2 # SjUKeym85VTOYGuY8b18fk5MQK2SzsfBUJ4x8VGC75W4mJ8agdc= # =HImO # -----END PGP SIGNATURE----- # gpg: Signature made Wed 31 Jan 2024 11:55:19 GMT # gpg: using RSA key 7B73BAD68BE7A2C289314B22701B4F6B1A693E59 # gpg: issuer "mjt@tls.msk.ru" # gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" [full] # gpg: aka "Michael Tokarev <mjt@corpit.ru>" [full] # gpg: aka "Michael Tokarev <mjt@debian.org>" [full] # Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D 4324 457C E0A0 8044 65C5 # Subkey fingerprint: 7B73 BAD6 8BE7 A2C2 8931 4B22 701B 4F6B 1A69 3E59 * tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu: (21 commits) hw/hyperv: Include missing headers hw/intc/xics: Include missing 'cpu.h' header hw/arm: Add `\n` to hint message hw/loongarch: Add `\n` to hint message hw/i386: Add `\n` to hint message backends/hostmem: Fix block comments style (checkpatch.pl warnings) misc: Clean up includes riscv: Clean up includes cxl: Clean up includes include: Clean up includes m68k: Clean up includes acpi: Clean up includes aspeed: Clean up includes disas/riscv: Clean up includes hyperv: Clean up includes scripts/clean-includes: Update exclude list mailmap: Fix Stefan Weil email qemu-docs: Update options for graphical frontends qapi/migration.json: Fix the member name for MigrationCapability colo: examples: remove mentions of script= and (wrong) downscript= ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-31Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into stagingPeter Maydell2-2/+16
Pull request # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCAAdFiEEhpWov9P5fNqsNXdanKSrs4Grc8gFAmW5b1IACgkQnKSrs4Gr # c8geoQf8DU8Z8jlvy1luuBZLq3R7hnC7c3Wzje0atLGP++pX6QUXfAgGDsTTIQeh # XWmkFhbOBurhToH8YpgPyNG8ZWYd9+NIvLnIJiWDklNDZg2zC00aOi8yBEbsgyFb # 50HJA30AAHq8PuctCzhGhENLxvBvNDNME74SwYH7FSIK5x/nA1XBHDZsjst1/Hk2 # 1loLbVWElbU28Xll7hI862SAb8RULC/sRQomkQAhpydxq4TApNuRwvpRfPNFwFJ0 # +dCquCJEfV6wfD62xg2CBGA5DrD9T7ADxmCYl4DQyp3HIRKXAptjgLsx3aZaIr1z # KAnCRNUXRuLgRZf7b9I+HhxGISoNng== # =/bBL # -----END PGP SIGNATURE----- # gpg: Signature made Tue 30 Jan 2024 21:51:14 GMT # gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [full] # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [full] # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * tag 'block-pull-request' of https://gitlab.com/stefanha/qemu: hw/block/block.c: improve confusing blk_check_size_and_read_all() error hw/core/qdev.c: add qdev_get_human_name() pflash: fix sectors vs bytes confusion in blk_pread_nonzeroes() block/blkio: Make s->mem_region_alignment be 64 bits block/io_uring: improve error message when init fails Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-30hw/block/block.c: improve confusing blk_check_size_and_read_all() errorManos Pitsidianakis1-2/+2
In cases where a device tries to read more bytes than the block device contains, the error is vague: "device requires X bytes, block backend provides Y bytes". This patch changes the errors of this function to include the block backend name, the device id and device type name where appropriate. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Message-id: 7260eadff22c08457740117c1bb7bd2b4353acb9.1706598705.git.manos.pitsidianakis@linaro.org Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-01-30hw/core/qdev.c: add qdev_get_human_name()Manos Pitsidianakis1-0/+14
Add a simple method to return some kind of human readable identifier for use in error messages. Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Message-id: 8b566bfced98ae44be1fcc1f8e7215f0c3393aa1.1706598705.git.manos.pitsidianakis@linaro.org Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-01-30include: Clean up includesPeter Maydell4-4/+0
This commit was created with scripts/clean-includes: ./scripts/clean-includes --git include include/*/*.h include/*/*/*.h All .c should include qemu/osdep.h first. The script performs three related cleanups: * Ensure .c files include qemu/osdep.h first. * Including it in a .h is redundant, since the .c already includes it. Drop such inclusions. * Likewise, including headers qemu/osdep.h includes is redundant. Drop these, too. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-01-30m68k: Clean up includesPeter Maydell2-2/+0
This commit was created with scripts/clean-includes: ./scripts/clean-includes --git m68k include/hw/audio/asc.h include/hw/m68k/*.h All .c should include qemu/osdep.h first. The script performs three related cleanups: * Ensure .c files include qemu/osdep.h first. * Including it in a .h is redundant, since the .c already includes it. Drop such inclusions. * Likewise, including headers qemu/osdep.h includes is redundant. Drop these, too. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-01-30acpi: Clean up includesPeter Maydell2-2/+0
This commit was created with scripts/clean-includes: ./scripts/clean-includes --git acpi include/hw/*/*acpi.h hw/*/*acpi.c All .c should include qemu/osdep.h first. The script performs three related cleanups: * Ensure .c files include qemu/osdep.h first. * Including it in a .h is redundant, since the .c already includes it. Drop such inclusions. * Likewise, including headers qemu/osdep.h includes is redundant. Drop these, too. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-01-29accel/tcg: Introduce TCGCPUOps::cpu_exec_halt() handlerPhilippe Mathieu-Daudé1-0/+2
In order to make accel/tcg/ target agnostic, introduce the cpu_exec_halt() handler. Reviewed-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240124101639.30056-9-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-01-29accel/tcg: Introduce TCGCPUOps::need_replay_interrupt() handlerPhilippe Mathieu-Daudé1-0/+5
In order to make accel/tcg/ target agnostic, introduce the need_replay_interrupt() handler. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Message-Id: <20240124101639.30056-7-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-01-29include/qemu: Add TCGCPUOps typedef to typedefs.hRichard Henderson1-4/+1
QEMU coding style recommends using structure typedefs. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-01-29include/hw/core: Remove i386 conditional on fake_user_interruptAnton Johansson1-3/+2
Always include fake_user_interrupt in user-only build, despite only being used for i386. This will enable cpu-exec.c to be compiled only once. Signed-off-by: Anton Johansson <anjo@rev.ng> Message-ID: <20240119144024.14289-18-anjo@rev.ng> [rth: Split out of a larger patch; remove TARGET_I386 conditional.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-01-29include/hw/core: Move do_interrupt in TCGCPUOpsAnton Johansson1-5/+2
The ifdef out of which it is moved is not quite right: do_interrupt is only needed for system mode. Move it to the top of a different ifdef block, which preserves its position within the structure for that case. Signed-off-by: Anton Johansson <anjo@rev.ng> Message-Id: <20240119144024.14289-18-anjo@rev.ng> [rth: Split from a larger patch and simplified.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-01-29hw/core: Include vaddr.h from cpu.hAnton Johansson1-1/+1
cpu-common.h is only needed for vaddr Signed-off-by: Anton Johansson <anjo@rev.ng> Message-Id: <20240119144024.14289-8-anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-01-26Merge tag 'pull-target-arm-20240126' of ↵Peter Maydell7-24/+62
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * Fix VNCR fault detection logic * Fix A64 scalar SQSHRN and SQRSHRN * Fix incorrect aa64_tidcp1 feature check * hw/arm/virt.c: Remove newline from error_report() string * hw/arm/musicpal: Convert to qemu_add_kbd_event_handler() * hw/arm/allwinner-a10: Unconditionally map the USB Host controllers * hw/arm/nseries: Unconditionally map the TUSB6010 USB Host controller * hw/arm: Add EHCI/OHCI controllers to Allwinner R40 and Bananapi board * hw/arm: Add AHCI/SATA controller to Allwinner R40 and Bananapi board * hw/arm: Add watchdog timer to Allwinner H40 and Bananapi board * arm: various include header cleanups * cleanups to allow some files to be built only once * fsl-imx6ul: Add various missing unimplemented devices * docs/system/arm/virt.rst: Add note on CPU features off by default * hw/char/imx_serial: Implement receive FIFO and ageing timer * target/xtensa: fix OOB TLB entry access * bswap.h: Fix const_le64() macro * hw/arm: add PCIe to Freescale i.MX6 # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmWzwpsZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3oTVD/4jM7ttKlXxtWsJ/cKDL5Im # uMmDECPrdK2qaNpONfV/YC3WadM6bSgB8OQd2YlI67DLgl3Hfaa+GnQsZhEgZ3lC # VECOTg5OKwwJY+Ac86t1GJa483wDEQ6NL08oLN94n9Ub/9G0S3oWpmE4bgof7PzW # rbLDDpKP+W5NfkqMfA5piV7N6mFHvg9wqFX//quqySIiu8NesKV9LmlP/FyNDU/s # 8ZeSqo/tq/IHr9IeYUtOoxVwYUOPuNKwD+vwy1taiXgjvVtq2URrCrlc4+KCWJsj # VUBSXdY2boqK31KFZ9NP9kJhIS5gmzgnK8YrHX6sgSbh+IybZUv+y/4eSO/LDYIi # r2VQF6oTtkmcIxUqAI6ZAehzZUIrB22QItUN8rg0slKBM8e/xHYaEBY8APKCLcvE # h59DLq1rPZG3Aie/h3/RjTfT2kI83PiE1mDGbhKf9G8UfXHEH8Eabd0g66UWfzlK # 67o7bwwzwXgoGk2hgMY/yobB3pF5YCly/a3aN/aLEj387y8sNaT1ASR9LETj7TC3 # xOhn5f8G6OFKMVI3K8Sco8ILP15LELprAW2keL4jn+4y3Hfq5yC984yOSnlM0wug # wWRvEr7U1ZiEbDaOvoa0beuYpeq1sm4OZ5yGJxGy3IuQ8pZpkHVTrBxw/NCNQnos # fK5czVTGqvvmPXgPsQQm1A== # =vYTy # -----END PGP SIGNATURE----- # gpg: Signature made Fri 26 Jan 2024 14:32:59 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20240126' of https://git.linaro.org/people/pmaydell/qemu-arm: (36 commits) hw/arm: add PCIe to Freescale i.MX6 target/arm: Fix incorrect aa64_tidcp1 feature check bswap.h: Fix const_le64() macro target/arm: Fix A64 scalar SQSHRN and SQRSHRN hw/char/imx_serial: Implement receive FIFO and ageing timer docs/system/arm/virt.rst: Add note on CPU features off by default fsl-imx6ul: Add various missing unimplemented devices hw/arm: Build various units only once target/arm: Move GTimer definitions to new 'gtimer.h' header target/arm: Move e2h_access() helper around target/arm: Move ARM_CPU_IRQ/FIQ definitions to 'cpu-qom.h' header hw/arm/armv7m: Make 'hw/intc/armv7m_nvic.h' a target agnostic header target/arm: Expose M-profile register bank index definitions hw/misc/xlnx-versal-crl: Build it only once hw/misc/xlnx-versal-crl: Include generic 'cpu-qom.h' instead of 'cpu.h' hw/cpu/a9mpcore: Build it only once target/arm: Declare ARM_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h' target/arm: Expose arm_cpu_mp_affinity() in 'multiprocessing.h' header target/arm: Create arm_cpu_mp_affinity target/arm: Rename arm_cpu_mp_affinity ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26hw/arm: add PCIe to Freescale i.MX6Nikita Ostrenkov1-21/+23
Signed-off-by: Nikita Ostrenkov <n.ostrenkov@gmail.com> Message-id: 20240108140325.1291-1-n.ostrenkov@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26hw/char/imx_serial: Implement receive FIFO and ageing timerRayhan Faizel1-1/+19
This patch implements a 32 half word FIFO as per imx serial device specifications. If a non empty FIFO is below the trigger level, an ageing timer will tick for a duration of 8 characters. On expiry, AGTIM will be set triggering an interrupt. AGTIM timer resets when there is activity in the receive FIFO. Otherwise, RRDY is set when trigger level is exceeded. The receive trigger level is 8 in newer kernel versions and 1 in older ones. This change will break migration compatibility for the imx boards. Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com> Message-id: 20240125151931.83494-1-rayhan.faizel@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: commit message tidyups] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26fsl-imx6ul: Add various missing unimplemented devicesGuenter Roeck1-0/+2
Add MMDC, OCOTP, SQPI, CAAM, and USBMISC as unimplemented devices. This allows operating systems such as Linux to run emulations such as mcimx6ul-evk. Before commit 0cd4926b85 ("Refactor i.MX6UL processor code"), the affected memory ranges were covered by the unimplemented DAP device. The commit reduced the DAP address range from 0x100000 to 4kB, and the emulation thus no longer covered the various unimplemented devices in the affected address range. Fixes: 0cd4926b85 ("Refactor i.MX6UL processor code") Cc: Jean-Christophe Dubois <jcd@tribudubois.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240120005356.2599547-1-linux@roeck-us.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-26hw/arm/armv7m: Make 'hw/intc/armv7m_nvic.h' a target agnostic headerPhilippe Mathieu-Daudé1-1/+1
Now than we can access the M-profile bank index definitions from the target-agnostic "cpu-qom.h" header, we don't need the huge "cpu.h" anymore (except in hw/arm/armv7m.c). Reduce its inclusion to the source unit. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-17-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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