aboutsummaryrefslogtreecommitdiff
path: root/include/hw
AgeCommit message (Collapse)AuthorFilesLines
2021-09-13hw/intc: GICv3 ITS Feature enablementShashi Mallela1-0/+1
Added properties to enable ITS feature and define qemu system address space memory in gicv3 common,setup distributor and redistributor registers to indicate LPI support. Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Message-id: 20210910143951.92242-6-shashi.mallela@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-13hw/intc: GICv3 ITS Command processingShashi Mallela1-0/+2
Added ITS command queue handling for MAPTI,MAPI commands,handled ITS translation which triggers an LPI via INT command as well as write to GITS_TRANSLATER register,defined enum to differentiate between ITS command interrupt trigger and GITS_TRANSLATER based interrupt trigger. Each of these commands make use of other functionalities implemented to get device table entry,collection table entry or interrupt translation table entry required for their processing. Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20210910143951.92242-5-shashi.mallela@linaro.org [PMM: use INTERRUPT for ItsCmdType enum name to avoid conflict with INT type defined by Windows headers] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-13hw/intc: GICv3 ITS register definitions addedShashi Mallela2-0/+26
Defined descriptors for ITS device table,collection table and ITS command queue entities.Implemented register read/write functions, extract ITS table parameters and command queue parameters,extended gicv3 common to capture qemu address space(which host the ITS table platform memories required for subsequent ITS processing) and initialize the same in ITS device. Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Message-id: 20210910143951.92242-3-shashi.mallela@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-13hw/intc: GICv3 ITS initial frameworkShashi Mallela1-1/+8
Added register definitions relevant to ITS,implemented overall ITS device framework with stubs for ITS control and translater regions read/write,extended ITS common to handle mmio init between existing kvm device and newer qemu device. Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Message-id: 20210910143951.92242-2-shashi.mallela@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-08mac_via: add qdev gpios for nubus slot interrupts to VIA2Mark Cave-Ayland1-0/+10
These will soon be required to enable nubus devices to support interrupts. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210830102447.10806-13-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-09-08mac_via: rename VIA2_IRQ_SLOT_BIT to VIA2_IRQ_NUBUS_BITMark Cave-Ayland1-11/+11
Also improve the alignment of the shifted constants. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210830102447.10806-12-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-09-08mac_via: remove mac_via deviceMark Cave-Ayland1-16/+5
Remove the mac_via device and wire up both q800 VIA1 and VIA2 directly for the m68k q800 machine. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210830102447.10806-10-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-09-08mac_via: move ADB variables to MOS6522Q800VIA1StateMark Cave-Ayland1-10/+10
The ADB is accessed using clock and data pins on q800 VIA1 port B and so can be moved to MOS6522Q800VIA1State. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210830102447.10806-6-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-09-08mac_via: move PRAM/RTC variables to MOS6522Q800VIA1StateMark Cave-Ayland1-11/+10
The PRAM/RTC is accessed using clock and data pins on q800 VIA1 port B and so can be moved to MOS6522Q800VIA1State. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210830102447.10806-5-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-09-08mac_via: move PRAM contents and block backend to MOS6522Q800VIA1StateMark Cave-Ayland1-3/+4
The PRAM contents are accessed using clock and data pins on q800 VIA1 port B and so can be moved to MOS6522Q800VIA1State. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210830102447.10806-4-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-09-06s390x: Replace PAGE_SIZE, PAGE_SHIFT and PAGE_MASKThomas Huth1-4/+1
The PAGE_SIZE macro is causing trouble on Alpine Linux since it clashes with a macro from a system header there. We already have the TARGET_PAGE_SIZE, TARGET_PAGE_MASK and TARGET_PAGE_BITS macros in QEMU anyway, so let's simply replace the PAGE_SIZE, PAGE_MASK and PAGE_SHIFT macro with their TARGET_* counterparts. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/572 Message-Id: <20210901125800.611183-1-thuth@redhat.com> Reviewed-by: Halil Pasic <pasic@linux.ibm.com> Reviewed-by: Matthew Rosato <mjrosato@linux.ibm.com> Reviewed-by: Eric Farman <farman@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-09-06hw/s390x/s390-skeys: lazy storage key enablement under TCGDavid Hildenbrand1-0/+63
Let's enable storage keys lazily under TCG, just as we do under KVM. Only fairly old Linux versions actually make use of storage keys, so it can be kind of wasteful to allocate quite some memory and track changes and references if nobody cares. We have to make sure to flush the TLB when enabling storage keys after the VM was already running: otherwise it might happen that we don't catch references or modifications afterwards. Add proper documentation to all callbacks. The kvm-unit-tests skey tests keeps on working with this change. Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210903155514.44772-14-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-09-06hw/s390x/s390-skeys: rename skeys_enabled to skeys_are_enabledDavid Hildenbrand1-1/+1
... and make it return a bool instead. Signed-off-by: David Hildenbrand <david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210903155514.44772-13-david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-09-06css: fix actl handling for unit exceptionsCornelia Huck1-1/+2
When a subchannel becomes pending with unit exception, start pending (and for that matter, halt or clear pending) are not removed in the actl. Device active and subchannel active, however, are (due to the subchannel becoming status pending with primary respectively secondary status). The other conditions in the actl are only cleared when the guest executes tsch on the subchannel. Signed-off-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Matthew Rosato <mjrosato@linux.ibm.com> Tested-by: Jared Rossi <jrossi@linux.ibm.com> Message-Id: <20210705163952.736020-3-cohuck@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2021-09-04vhost: use unsigned int for nvqsJason Wang1-1/+1
Switch to use unsigned int for nvqs since it's not expected to be negative. Reviewed-by: Eli Cohen <elic@nvidia.com> Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20210903091031.47303-5-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-09-04hw/pci: remove all references to find_i440fx functionAni Sinha1-1/+0
commit c0e427d6eb5fefc538 ("hw/acpi/ich9: Enable ACPI PCI hot-plug") removed all uses of find_i440fx() function. This has been replaced by the more generic call acpi_get_i386_pci_host() which maybe able to find the root bus both for i440fx machine type as well as for the q35 machine type. There seems to be no more any need to maintain a i440fx specific version of the api call. Remove it. Tested by building from a clean tree successfully. Signed-off-by: Ani Sinha <ani@anisinha.ca> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210825031949.919376-2-ani@anisinha.ca> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-09-04hw/i386/acpi-build: Get NUMA information from struct NumaStateJingqi Liu1-4/+0
Since commits aa57020774b ("numa: move numa global variable nb_numa_nodes into MachineState") and 7e721e7b10e ("numa: move numa global variable numa_info into MachineState"), we can get NUMA information completely from MachineState::numa_state. Remove PCMachineState::numa_nodes and PCMachineState::node_mem, since they are just copied from MachineState::numa_state. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Jingqi Liu <jingqi.liu@intel.com> Message-Id: <20210823011254.28506-1-jingqi.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-09-04virtio-bus: introduce iommu_enabled()Jason Wang1-1/+3
This patch introduce a new method for the virtio-bus for the transport to report whether or not the IOMMU is enabled for the device. Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20210804034803.1644-2-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-09-04acpi: Delete broken ACPI_GED_X86 macroEduardo Habkost1-2/+0
The macro never worked and never will, because the AcpiGedX86State type never existed. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20210805193431.307761-2-ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-09-04hw/virtio: move vhost_set_backend_type() to vhost.cTiberiu Georgescu2-6/+4
Just a small refactor patch. vhost_set_backend_type() gets called only in vhost.c, so we can move the function there and make it static. We can then extern the visibility of kernel_ops, to match the other VhostOps in vhost-backend.h. The VhostOps constants now make more sense in vhost.h Suggested-by: Raphael Norwitz <raphael.norwitz@nutanix.com> Signed-off-by: Tiberiu Georgescu <tiberiu.georgescu@nutanix.com> Message-Id: <20210809134015.67941-1-tiberiu.georgescu@nutanix.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-09-04hw/acpi: define PIIX4 acpi pci hotplug property strings at a single placeAni Sinha1-0/+2
Now that we have "acpi-pci-hotplug-with-bridge-support" PIIX4 PM property being used for both q35 and i440fx machine types, it is better that we defined this property string at a single place within a header file like other PIIX4 properties. We can then use this single definition at all the places that needs it instead of duplicating the string everywhere. While at it, this change also adds a definition for "acpi-root-pci-hotplug" PIIX4 PM property and uses this definition at all places that were formally using the string value. Signed-off-by: Ani Sinha <ani@anisinha.ca> Message-Id: <20210816083214.105740-1-ani@anisinha.ca> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-09-04vhost-vdpa: Do not send empty IOTLB update batchesEugenio Pérez1-0/+1
With the introduction of the batch hinting, meaningless batches can be created with no IOTLB updates if the memory region was skipped by vhost_vdpa_listener_skipped_section. This is the case of host notifiers memory regions, device un/realize, and others. This causes the vdpa device to receive dma mapping settings with no changes, a possibly expensive operation for nothing. To avoid that, VHOST_IOTLB_BATCH_BEGIN hint is delayed until we have a meaningful (not skipped section) mapping or unmapping operation, and VHOST_IOTLB_BATCH_END is not written unless at least one of _UPDATE / _INVALIDATE has been issued. v3: * Use a bool instead of a counter avoiding potential number wrapping * Fix bad check on _commit * Move VHOST_BACKEND_F_IOTLB_BATCH check to vhost_vdpa_iotlb_batch_begin_once v2 (from RFC): * Rename misleading name * Abstract start batching function for listener_add/del Signed-off-by: Eugenio Pérez <eperezma@redhat.com> Message-Id: <20210812140933.226288-1-eperezma@redhat.com> Acked-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-09-02Merge remote-tracking branch 'remotes/hreitz/tags/pull-block-2021-09-01' ↵Peter Maydell1-0/+1
into staging Block patches: - Make the backup-top filter driver available for user-created block nodes (i.e. via blockdev-add) - Allow running iotests with gdb or valgrind being attached to qemu instances - Fix the raw format driver's permissions: There is no metadata, so we only need WRITE or RESIZE when the parent needs it - Basic reopen implementation for win32 files (file-win32.c) so that qemu-img commit can work - uclibc/musl build fix for the FUSE export code - Some iotests delinting - block-hmp-cmds.c refactoring # gpg: Signature made Wed 01 Sep 2021 16:01:54 BST # gpg: using RSA key CB62D7A0EE3829E45F004D34A1FA40D098019CDF # gpg: issuer "hreitz@redhat.com" # gpg: Good signature from "Hanna Reitz <hreitz@redhat.com>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: CB62 D7A0 EE38 29E4 5F00 4D34 A1FA 40D0 9801 9CDF * remotes/hreitz/tags/pull-block-2021-09-01: (56 commits) block/file-win32: add reopen handlers block/export/fuse.c: fix fuse-lseek on uclibc or musl block/block-copy: block_copy_state_new(): drop extra arguments iotests/image-fleecing: add test-case for copy-before-write filter iotests/image-fleecing: prepare for adding new test-case iotests/image-fleecing: rename tgt_node iotests/image-fleecing: proper source device iotests.py: hmp_qemu_io: support qdev iotests: move 222 to tests/image-fleecing iotests/222: constantly use single quotes for strings iotests/222: fix pylint and mypy complains python:QEMUMachine: template typing for self returning methods python/qemu/machine: QEMUMachine: improve qmp() method python/qemu/machine.py: refactor _qemu_args() qapi: publish copy-before-write filter block/copy-before-write: make public block driver block/block-copy: make setting progress optional block/copy-before-write: initialize block-copy bitmap block/copy-before-write: cbw_init(): use options block/copy-before-write: bdrv_cbw_append(): drop unused compress arg ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-01qdev-properties: PropertyInfo: add realized_set_allowed fieldVladimir Sementsov-Ogievskiy1-0/+1
Add field, so property can declare support for setting the property when device is realized. To be used in the following commit. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-Id: <20210824083856.17408-4-vsementsov@virtuozzo.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
2021-09-01arm: Remove system_clock_scale globalPeter Maydell1-22/+0
All the devices that used to use system_clock_scale have now been converted to use Clock inputs instead, so the global is no longer needed; remove it and all the code that sets it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210812093356.1946-26-peter.maydell@linaro.org
2021-09-01hw/timer/stellaris-gptm: Use Clock input instead of system_clock_scalePeter Maydell1-0/+3
The stellaris-gptm timer currently uses system_clock_scale for one of its timer modes where the timer runs at the CPU clock rate. Make it use a Clock input instead. We don't try to make the timer handle changes in the clock frequency while the downcounter is running. This is not a change in behaviour from the previous system_clock_scale implementation -- we will pick up the new frequency only when the downcounter hits zero. Handling dynamic clock changes when the counter is running would require state that the current gptm implementation doesn't have. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Message-id: 20210812093356.1946-25-peter.maydell@linaro.org
2021-09-01hw/arm/stellaris: Split stellaris-gptm into its own filePeter Maydell1-0/+48
The implementation of the Stellaris general purpose timer module device stellaris-gptm is currently in the same source file as the board model. Split it out into its own source file in hw/timer. Apart from the new file comment headers and the Kconfig and meson.build changes, this is just code movement. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Message-id: 20210812093356.1946-24-peter.maydell@linaro.org
2021-09-01hw/arm/msf2-soc: Wire up refclkPeter Maydell1-0/+1
Wire up the refclk for the msf2 SoC. This SoC runs the refclk at a frequency which is programmably either /4, /8, /16 or /32 of the main CPU clock. We don't currently model the register which allows the guest to set the divisor, so implement the refclk as a fixed /32 of the CPU clock (which is the value of the divisor at reset). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Message-id: 20210812093356.1946-21-peter.maydell@linaro.org
2021-09-01hw/arm/msf2: Use Clock input to MSF2_SOC instead of m3clk propertyPeter Maydell1-1/+2
Instead of passing the MSF2 SoC an integer property specifying the CPU clock rate, pass it a Clock instead. This lets us wire that clock up to the armv7m object. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Message-id: 20210812093356.1946-20-peter.maydell@linaro.org
2021-09-01hw/arm/msf2_soc: Don't allocate separate MemoryRegionsPeter Maydell1-0/+4
In the realize method of the msf2-soc SoC object, we call g_new() to create new MemoryRegion objects for the nvm, nvm_alias, and sram. This is unnecessary; make these MemoryRegions member fields of the device state struct instead. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Message-id: 20210812093356.1946-19-peter.maydell@linaro.org
2021-09-01hw/arm/nrf51: Wire up sysclkPeter Maydell1-0/+2
Wire up the sysclk input to the armv7m object. Strictly this SoC should not have a systick device at all, but our armv7m container object doesn't currently support disabling the systick device. For the moment, add a TODO comment, but note that this is why we aren't wiring up a refclk (no need for one). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Message-id: 20210812093356.1946-16-peter.maydell@linaro.org
2021-09-01hw/arm/stm32f405: Wire up sysclk and refclkPeter Maydell1-0/+3
Wire up the sysclk and refclk for the stm32f405 SoC. This SoC always runs the systick refclk at 1/8 the frequency of the main CPU clock, so the board code only needs to provide a single sysclk clock. Because there is only one board using this SoC, we convert the SoC and the board together, rather than splitting it into "add clock to SoC; connect clock in board; add error check in SoC code that clock is wired up". When the systick device starts honouring its clock inputs, this will fix an emulation inaccuracy in the netduinoplus2 board where the systick reference clock was running at 1MHz rather than 21MHz. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-14-peter.maydell@linaro.org
2021-09-01hw/arm/stm32f205: Wire up sysclk and refclkPeter Maydell1-0/+4
Wire up the sysclk and refclk for the stm32f205 SoC. This SoC always runs the systick refclk at 1/8 the frequency of the main CPU clock, so the board code only needs to provide a single sysclk clock. Because there is only one board using this SoC, we convert the SoC and the board together, rather than splitting it into "add clock to SoC; connect clock in board; add error check in SoC code that clock is wired up". When the systick device starts honouring its clock inputs, this will fix an emulation inaccuracy in the netduino2 board where the systick reference clock was running at 1MHz rather than 15MHz. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-13-peter.maydell@linaro.org
2021-09-01hw/arm/stm32f100: Wire up sysclk and refclkPeter Maydell1-0/+4
Wire up the sysclk and refclk for the stm32f100 SoC. This SoC always runs the systick refclk at 1/8 the frequency of the main CPU clock, so the board code only needs to provide a single sysclk clock. Because there is only one board using this SoC, we convert the SoC and the board together, rather than splitting it into "add clock to SoC; connect clock in board; add error check in SoC code that clock is wired up". When the systick device starts honouring its clock inputs, this will fix an emulation inaccuracy in the stm32vldiscovery board where the systick reference clock was running at 1MHz rather than 3MHz. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-12-peter.maydell@linaro.org
2021-09-01hw/arm: Don't allocate separate MemoryRegions in stm32 SoC realizePeter Maydell2-0/+8
In the realize methods of the stm32f100 and stm32f205 SoC objects, we call g_new() to create new MemoryRegion objects for the sram, flash, and flash_alias. This is unnecessary (and leaves open the possibility of leaking the allocations if we exit from realize with an error). Make these MemoryRegions member fields of the device state struct instead, as stm32f405 already does. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-11-peter.maydell@linaro.org
2021-09-01clock: Provide builtin multiplier/dividerPeter Maydell1-0/+29
It is quite common for a clock tree to involve possibly programmable clock multipliers or dividers, where the frequency of a clock is for instance divided by 8 to produce a slower clock to feed to a particular device. Currently we provide no convenient mechanism for modelling this. You can implement it by having an input Clock and an output Clock, and manually setting the period of the output clock in the period-changed callback of the input clock, but that's quite clunky. This patch adds support in the Clock objects themselves for setting a multiplier or divider. The effect of setting this on a clock is that when the clock's period is changed, all the children of the clock are set to period * multiplier / divider, rather than being set to the same period as the parent clock. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Message-id: 20210812093356.1946-10-peter.maydell@linaro.org
2021-09-01hw/arm/armv7m: Create input clocksPeter Maydell1-0/+6
Create input clocks on the armv7m container object which pass through to the systick timers, so that users of the armv7m object can specify the clocks being used. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-7-peter.maydell@linaro.org
2021-09-01hw/timer/armv7m_systick: Add input clocksPeter Maydell1-0/+7
The v7M systick timer can be programmed to run from either of two clocks: * an "external reference clock" (when SYST_CSR.CLKSOURCE == 0) * the main CPU clock (when SYST_CSR.CLKSOURCE == 1) Our implementation currently hardwires the external reference clock to be 1MHz, and allows boards to set the main CPU clock frequency via the global 'system_clock_scale'. (Most boards set that to a constant value; the Stellaris boards allow the guest to reprogram it via the board-specific RCC registers). As the first step in converting this to use the Clock infrastructure, add input clocks to the systick device for the reference clock and the CPU clock. The device implementation ignores them; once we have made all the users of the device correctly wire up the new Clocks we will switch the implementation to use them and ignore the old system_clock_scale. This is a migration compat break for all M-profile boards, because of the addition of the new clock objects to the vmstate struct. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-6-peter.maydell@linaro.org
2021-09-01hw/timer/armv7m_systick: Add usual QEMU interface commentPeter Maydell1-0/+7
Add the usual-style QEMU interface comment documenting what properties, etc, this device exposes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-5-peter.maydell@linaro.org
2021-09-01arm: Move system PPB container handling to armv7mPeter Maydell2-3/+4
Instead of having the NVIC device provide a single sysbus memory region covering the whole of the "System PPB" space, which implements the default behaviour for unimplemented ranges and provides the NS alias window to the sysregs as well as the main sysreg MR, move this handling to the container armv7m device. The NVIC now provides a single memory region which just implements the system registers. This consolidates all the handling of "map various devices in the PPB" into the armv7m container where it belongs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-4-peter.maydell@linaro.org
2021-09-01arm: Move systick device creation from NVIC to ARMv7M objectPeter Maydell2-4/+12
There's no particular reason why the NVIC should be owning the SysTick device objects; move them into the ARMv7M container object instead, as part of consolidating the "create the devices which are built into an M-profile CPU and map them into their architected locations in the address space" work into one place. This involves temporarily creating a duplicate copy of the nvic_sysreg_ns_ops struct and its read/write functions (renamed as v7m_sysreg_ns_*), but we will delete the NVIC's copy of this code in a subsequent patch. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-3-peter.maydell@linaro.org
2021-09-01arm: Move M-profile RAS register block into its own devicePeter Maydell3-1/+39
Currently we implement the RAS register block within the NVIC device. It isn't really very tightly coupled with the NVIC proper, so instead move it out into a sysbus device of its own and have the top level ARMv7M container create it and map it into memory at the right address. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Message-id: 20210812093356.1946-2-peter.maydell@linaro.org
2021-09-01hw: Add compat machines for 6.2Yanan Wang2-0/+6
Add 6.2 machine types for arm/i440fx/q35/s390x/spapr. Signed-off-by: Yanan Wang <wangyanan55@huawei.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Pankaj Gupta <pankaj.gupta@ionos.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-01hw/registerfields: Use 64-bit bitfield for FIELD_DP64Joe Komlodi1-1/+1
If we have a field that's wider than 32-bits, we need a data type wide enough to be able to create the bitfield used to deposit the value. Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1626805903-162860-3-git-send-email-joe.komlodi@xilinx.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-01hw/core/register: Add more 64-bit utilitiesJoe Komlodi2-0/+16
We already have some utilities to handle 64-bit wide registers, so this just adds some more for: - Initializing 64-bit registers - Extracting and depositing to an array of 64-bit registers Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1626805903-162860-2-git-send-email-joe.komlodi@xilinx.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-08-27ppc/xive: Export xive_presenter_notify()Cédric Le Goater1-0/+4
It's generic enough to be used from the XIVE2 router and avoid more duplication. Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210809134547.689560-9-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-08-27ppc/xive: Export PQ get/set routinesCédric Le Goater1-0/+4
These will be shared with the XIVE2 router. Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210809134547.689560-8-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-08-27ppc/pnv: Use a simple incrementing index for the chip-idCédric Le Goater1-26/+7
When the QEMU PowerNV machine was introduced, multi chip support modeled a two socket system with dual chip modules as found on some P8 Tuleta systems (8286-42A). But this is hardly used and not relevant for QEMU. Use a simple index instead. With this change, we can now increase the max socket number to 16 as found on high end systems. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210809134547.689560-5-clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-08-27ppc/pnv: Change the POWER10 machine to support DD2 onlyCédric Le Goater1-1/+1
There is no need to keep the DD1 chip model as it will never be publicly available. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210809134547.689560-3-clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2021-08-26hw/arm/xlnx-zynqmp: Add unimplemented APU mmioTong Ho1-0/+7
Add unimplemented APU mmio region to xlnx-zynqmp for booting bare-metal guests built with standalone bsp, which access the region from one of the following places: https://github.com/Xilinx/embeddedsw/blob/release-2020.2/lib/bsp/standalone/src/arm/ARMv8/64bit/armclang/boot.S#L139 https://github.com/Xilinx/embeddedsw/blob/release-2020.2/lib/bsp/standalone/src/arm/ARMv8/64bit/gcc/boot.S#L183 Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Tong Ho <tong.ho@xilinx.com> Message-id: 20210823173818.201259-3-tong.ho@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.1 at 2025-02-08 02:46:32 +0000