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path: root/include/hw/riscv/microchip_pfsoc.h
AgeCommit message (Expand)AuthorFilesLines
2023-01-06hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0Bin Meng1-1/+1
2023-01-06hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLICBin Meng1-1/+1
2023-01-06hw/{misc, riscv}: pfsoc: add system controller as unimplementedConor Dooley1-0/+1
2023-01-06hw/riscv: pfsoc: add missing FICs as unimplementedConor Dooley1-0/+2
2022-09-07hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripheralsConor Dooley1-1/+13
2021-10-28hw/riscv: microchip_pfsoc: Use the PLIC config helper functionAlistair Francis1-1/+0
2021-03-22hw/riscv: microchip_pfsoc: Map EMMC/SD mux registerBin Meng1-0/+1
2020-12-17hw/riscv: microchip_pfsoc: add QSPI NOR flashVitaly Wool1-0/+3
2020-11-03hw/riscv: microchip_pfsoc: Hook the I2C1 controllerBin Meng1-0/+1
2020-11-03hw/riscv: microchip_pfsoc: Correct DDR memory mapBin Meng1-1/+4
2020-11-03hw/riscv: microchip_pfsoc: Map the reserved memory at address 0Bin Meng1-0/+1
2020-11-03hw/riscv: microchip_pfsoc: Connect the SYSREG moduleBin Meng1-0/+2
2020-11-03hw/riscv: microchip_pfsoc: Connect the IOSCB moduleBin Meng1-1/+3
2020-11-03hw/riscv: microchip_pfsoc: Connect DDR memory controller modulesBin Meng1-0/+5
2020-09-09hw/riscv: microchip_pfsoc: Hook GPIO controllersBin Meng1-0/+3
2020-09-09hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMsBin Meng1-0/+7
2020-09-09hw/riscv: microchip_pfsoc: Connect a DMA controllerBin Meng1-0/+11
2020-09-09hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD cardBin Meng1-0/+4
2020-09-09hw/riscv: microchip_pfsoc: Connect 5 MMUARTsBin Meng1-0/+20
2020-09-09hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit boardBin Meng1-0/+88
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