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path: root/include/exec/exec-all.h
AgeCommit message (Expand)AuthorFilesLines
2019-12-16tcg: cputlb: Add probe_readBeata Michalska1-0/+6
2019-10-28include/exec: wrap cpu_ldst.h in CONFIG_TCGAlex Bennée1-0/+2
2019-10-28cputlb: introduce get_page_addr_code_hostpEmilio G. Cota1-0/+38
2019-10-28cputlb: document get_page_addr_codeEmilio G. Cota1-3/+21
2019-10-10s390x/tcg: MVCL: Exit to main loop if requestedDavid Hildenbrand1-0/+17
2019-09-25cputlb: Partially inline memory_region_section_get_iotlbRichard Henderson1-5/+1
2019-09-03tcg: Factor out probe_write() logic into probe_access()David Hildenbrand1-2/+8
2019-09-03tcg: Make probe_write() return a pointer to the host pageDavid Hildenbrand1-2/+2
2019-09-03tcg: Factor out CONFIG_USER_ONLY probe_write() from s390x codeDavid Hildenbrand1-2/+2
2019-08-16include: Make headers more self-containedMarkus Armbruster1-0/+1
2019-06-12Include qemu-common.h exactly where neededMarkus Armbruster1-1/+0
2019-05-10tcg: Use CPUClass::tlb_fill in cputlb.cRichard Henderson1-9/+0
2019-04-24tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson1-2/+2
2019-02-11exec-all: document that tlb_fill can trigger a TLB resizeEmilio G. Cota1-0/+5
2019-01-29accel/tcg: Add cluster number to TCG TB hashPeter Maydell1-1/+3
2018-10-18exec: introduce tlb_initEmilio G. Cota1-0/+8
2018-08-14accel/tcg: Check whether TLB entry is RAM consistently with how we set it upPeter Maydell1-2/+0
2018-07-02tcg: simplify !CONFIG_TCG handling of tb_invalidate_*Paolo Bonzini1-5/+3
2018-07-02tcg: Fix --disable-tcg build breakagePhilippe Mathieu-Daudé1-4/+9
2018-06-28move public invalidate APIs out of translate-all.{c,h}, clean upPaolo Bonzini1-4/+4
2018-06-15tcg: remove tb_lockEmilio G. Cota1-4/+0
2018-06-15translate-all: protect TB jumps with a per-destination-TB lockEmilio G. Cota1-13/+22
2018-06-15translate-all: introduce assert_no_pages_lockedEmilio G. Cota1-0/+8
2018-06-15translate-all: use per-page locking in !user-modeEmilio G. Cota1-1/+2
2018-06-15translate-all: iterate over TBs in a page with PAGE_FOR_EACH_TBEmilio G. Cota1-1/+1
2018-06-15tcg: track TBs with per-region BST'sEmilio G. Cota1-1/+0
2018-06-15exec.c: Handle IOMMUs in address_space_translate_for_iotlb()Peter Maydell1-1/+2
2018-06-15cputlb: Pass cpu_transaction_failed() the correct physaddrPeter Maydell1-2/+11
2018-05-31Make tb_invalidate_phys_addr() take a MemTxAttrs argumentPeter Maydell1-2/+3
2018-04-11icount: fix cpu_restore_state_from_tb for non-tb-exit casesPavel Dovgalyuk1-1/+4
2018-01-25accel/tcg: add size paremeter in tlb_fill()Laurent Vivier1-3/+3
2017-12-21cpu: refactor cpu_address_space_init()Peter Xu1-2/+4
2017-11-13accel/tcg/translate-all: expand cpu_restore_state addr checkAlex Bennée1-0/+11
2017-10-24exec-all: rename tb_free to tb_removeEmilio G. Cota1-1/+1
2017-10-24translate-all: use a binary search tree to track TBs in TBContextEmilio G. Cota1-1/+5
2017-10-24tcg: Remove CF_IGNORE_ICOUNTRichard Henderson1-8/+9
2017-10-24tcg: Add CF_LAST_IO + CF_USE_ICOUNT to CF_HASH_MASKRichard Henderson1-1/+2
2017-10-24tcg: Include CF_COUNT_MASK in CF_HASH_MASKRichard Henderson1-1/+1
2017-10-24tcg: define CF_PARALLEL and use it for TB hashing along with CF_COUNT_MASKEmilio G. Cota1-1/+19
2017-10-10exec-all: extract tb->tc_* into a separate struct tc_tbEmilio G. Cota1-2/+10
2017-10-10exec-all: introduce TB_PAGE_ADDR_FMTEmilio G. Cota1-0/+2
2017-10-10exec-all: bring tb->invalid into tb->cflagsEmilio G. Cota1-2/+1
2017-10-10exec-all: fix typos in TranslationBlock's documentationEmilio G. Cota1-2/+2
2017-09-07tcg: Move USE_DIRECT_JUMP discriminator to tcg/cpu/tcg-target.hRichard Henderson1-92/+3
2017-09-06target: [tcg] Use a generic enum for DISAS_ valuesLluís Vilanova1-30/+0
2017-09-06tcg: Add generic DISAS_NORETURNRichard Henderson1-0/+1
2017-07-19tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova1-1/+1
2017-07-18Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170717'...Peter Maydell1-3/+26
2017-07-17include/exec/exec-all: document common exit conditionsAlex Bennée1-3/+26
2017-07-17exec: [tcg] Use different TBs according to the vCPU's dynamic tracing stateLluís Vilanova1-0/+3
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