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path: root/include/exec/exec-all.h
AgeCommit message (Expand)AuthorFilesLines
2021-09-21include/exec: Move cpu_signal_handler declarationRichard Henderson1-0/+13
2021-07-21accel/tcg: Record singlestep_enabled in tb->cflagsRichard Henderson1-0/+1
2021-07-21accel/tcg: Add CF_NO_GOTO_TB and CF_NO_GOTO_PTRRichard Henderson1-7/+9
2021-07-21accel/tcg: Move curr_cflags into cpu-exec.cRichard Henderson1-4/+1
2021-07-21accel/tcg: Reduce CF_COUNT_MASK to match TCG_MAX_INSNSRichard Henderson1-1/+3
2021-05-26accel/tcg: Reduce 'exec/tb-context.h' inclusionPhilippe Mathieu-Daudé1-1/+0
2021-05-25accel/tlb: Add tlb_flush_range_by_mmuidx_all_cpus_synced()Richard Henderson1-0/+12
2021-05-25accel/tcg: Add tlb_flush_range_by_mmuidx_all_cpus()Richard Henderson1-0/+13
2021-05-25accel/tcg: Add tlb_flush_range_by_mmuidx()Richard Henderson1-0/+19
2021-03-06accel/tcg: Precompute curr_cflags into cpu->tcg_cflagsRichard Henderson1-6/+1
2021-03-06include/exec: lightly re-arrange TranslationBlockAlex Bennée1-3/+8
2021-03-06accel/tcg: drop the use of CF_HASH_MASK and rename paramsAlex Bennée1-3/+1
2021-03-06accel/tcg: move CF_CLUSTER calculation to curr_cflagsAlex Bennée1-3/+5
2021-02-18accel/tcg: allow plugin instrumentation to be disable via cflagsAlex Bennée1-3/+3
2021-02-18accel/tcg: remove CF_NOCACHE and special casesAlex Bennée1-3/+0
2021-02-16exec: Use cpu_untagged_addr in g2h; split out g2h_untaggedRichard Henderson1-1/+1
2021-02-05tcg/tci: Make tci_tb_ptr thread-localRichard Henderson1-1/+1
2021-01-23accel/tcg: Restrict cpu_io_recompile() from other acceleratorsPhilippe Mathieu-Daudé1-1/+0
2021-01-23accel/tcg: Restrict tb_gen_code() from other acceleratorsPhilippe Mathieu-Daudé1-5/+0
2021-01-23accel/tcg: Move tb_flush_jmp_cache() to cputlb.cRichard Henderson1-3/+0
2021-01-23accel/tcg: Make cpu_gen_init() staticPhilippe Mathieu-Daudé1-2/+0
2021-01-07tcg: Introduce tcg_splitwx_to_{rx,rw}Richard Henderson1-1/+1
2020-12-15vl: extract softmmu/globals.cPaolo Bonzini1-3/+0
2020-11-15overall/alpha tcg cpus|hppa: Fix Lesser GPL version numberChetan Pant1-1/+1
2020-10-20accel/tcg: Add tlb_flush_page_bits_by_mmuidx*Richard Henderson1-0/+36
2020-10-05cpu-timers, icount: new modulesClaudio Fontana1-2/+2
2020-09-23qemu/atomic.h: rename atomic_ to qatomic_Stefan Hajnoczi1-3/+3
2020-06-16cputlb: destroy CPUTLB with tlb_destroyEmilio G. Cota1-0/+8
2020-05-11accel/tcg: Add probe_access_flagsRichard Henderson1-0/+22
2020-05-11accel/tcg: Add block comment for probe_accessRichard Henderson1-0/+17
2019-12-16tcg: cputlb: Add probe_readBeata Michalska1-0/+6
2019-10-28include/exec: wrap cpu_ldst.h in CONFIG_TCGAlex Bennée1-0/+2
2019-10-28cputlb: introduce get_page_addr_code_hostpEmilio G. Cota1-0/+38
2019-10-28cputlb: document get_page_addr_codeEmilio G. Cota1-3/+21
2019-10-10s390x/tcg: MVCL: Exit to main loop if requestedDavid Hildenbrand1-0/+17
2019-09-25cputlb: Partially inline memory_region_section_get_iotlbRichard Henderson1-5/+1
2019-09-03tcg: Factor out probe_write() logic into probe_access()David Hildenbrand1-2/+8
2019-09-03tcg: Make probe_write() return a pointer to the host pageDavid Hildenbrand1-2/+2
2019-09-03tcg: Factor out CONFIG_USER_ONLY probe_write() from s390x codeDavid Hildenbrand1-2/+2
2019-08-16include: Make headers more self-containedMarkus Armbruster1-0/+1
2019-06-12Include qemu-common.h exactly where neededMarkus Armbruster1-1/+0
2019-05-10tcg: Use CPUClass::tlb_fill in cputlb.cRichard Henderson1-9/+0
2019-04-24tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson1-2/+2
2019-02-11exec-all: document that tlb_fill can trigger a TLB resizeEmilio G. Cota1-0/+5
2019-01-29accel/tcg: Add cluster number to TCG TB hashPeter Maydell1-1/+3
2018-10-18exec: introduce tlb_initEmilio G. Cota1-0/+8
2018-08-14accel/tcg: Check whether TLB entry is RAM consistently with how we set it upPeter Maydell1-2/+0
2018-07-02tcg: simplify !CONFIG_TCG handling of tb_invalidate_*Paolo Bonzini1-5/+3
2018-07-02tcg: Fix --disable-tcg build breakagePhilippe Mathieu-Daudé1-4/+9
2018-06-28move public invalidate APIs out of translate-all.{c,h}, clean upPaolo Bonzini1-4/+4
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