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2023-01-09exec/memory: Expose memory_region_access_valid()Philippe Mathieu-Daudé1-1/+1
2023-01-07Merge tag 'pull-loongarch-20230106' of https://gitlab.com/gaosong/qemu into s...Peter Maydell3-14/+69
2023-01-06Merge tag 'pull-riscv-to-apply-20230106' of https://github.com/alistair23/qem...Peter Maydell10-107/+238
2023-01-06Merge tag 'pull-tcg-20230105' of https://gitlab.com/rth7680/qemu into stagingPeter Maydell3-19/+3
2023-01-06hw/intc/loongarch_pch: Change default irq number of pch irq controllerTianrui Zhao2-2/+3
2023-01-06hw/intc/loongarch_pch_pic: add irq number propertyTianrui Zhao2-7/+35
2023-01-06hw/intc/loongarch_pch_msi: add irq number propertyTianrui Zhao2-8/+34
2023-01-06hw/intc: sifive_plic: Fix the pending register range checkBin Meng1-2/+3
2023-01-06hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initializationBin Meng1-2/+0
2023-01-06hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0Bin Meng1-2/+3
2023-01-06hw/riscv: virt: Fix the value of "riscv, ndev" in the dtbBin Meng1-1/+2
2023-01-06hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"Bin Meng1-1/+2
2023-01-06hw/intc: sifive_plic: Update "num-sources" property default valueBin Meng1-1/+7
2023-01-06hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in ...Bin Meng1-3/+4
2023-01-06hw/intc: sifive_plic: Improve robustness of the PLIC config parserBin Meng1-8/+16
2023-01-06hw/intc: sifive_plic: Drop PLICMode_HBin Meng1-1/+0
2023-01-06hw/riscv: spike: Remove misleading commentsBin Meng1-1/+0
2023-01-06hw/riscv: Sort machines Kconfig options in alphabetical orderBin Meng1-7/+9
2023-01-06hw/riscv: Fix opentitan dependency to SIFIVE_PLICBin Meng1-0/+1
2023-01-06hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllersBin Meng1-0/+2
2023-01-06hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLICBin Meng2-5/+1
2023-01-06hw/intc: sifive_plic: fix out-of-bound access of source_priority arrayJim Shu1-1/+11
2023-01-06hw/{misc, riscv}: pfsoc: add system controller as unimplementedConor Dooley3-6/+90
2023-01-06hw/riscv: pfsoc: add missing FICs as unimplementedConor Dooley1-52/+63
2023-01-06hw/misc: pfsoc: add fabric clocks to ioscbConor Dooley1-0/+6
2023-01-06hw/riscv: virt: Remove the redundant ipi-id propertyAtish Patra1-4/+0
2023-01-06hw/intc: sifive_plic: Renumber the S irqs for numa supportFrédéric Pétrot1-2/+2
2023-01-06hw/riscv/opentitan: add aon_timer base unimplWilfred Mallawa1-0/+3
2023-01-06hw/riscv/opentitan: bump opentitanWilfred Mallawa1-8/+13
2023-01-05Merge tag 'pull-target-arm-20230105' of https://git.linaro.org/people/pmaydel...Peter Maydell11-197/+352
2023-01-05accel/tcg: Set cflags_next_tb in cpu_common_initfnRichard Henderson1-0/+1
2023-01-05hw/net: Fix read of uninitialized memory in imx_fec.Stephen Longfield1-4/+4
2023-01-05i.MX7D: Connect IRQs to GPIO devices.Jean-Christophe Dubois1-1/+30
2023-01-05i.MX6UL: Add a specific GPT timer instance for the i.MX6ULJean-Christophe Dubois3-7/+26
2023-01-05i.MX7D: Compute clock frequency for the fixed frequency clocks.Jean-Christophe Dubois1-9/+40
2023-01-05i.MX7D: Connect GPT timers to IRQJean-Christophe Dubois1-0/+10
2023-01-05hw/arm/smmu-common: Avoid using inlined functions with external linkagePhilippe Mathieu-Daudé1-7/+6
2023-01-05hw/arm/smmu-common: Reduce smmu_inv_notifiers_mr() scopePhilippe Mathieu-Daudé1-1/+1
2023-01-05hw/arm/nseries: Silent -Wmissing-field-initializers warningPhilippe Mathieu-Daudé1-6/+4
2023-01-05hw/arm/nseries: Constify various read-only arraysPhilippe Mathieu-Daudé1-9/+9
2023-01-05hw/input/tsc2xxx: Constify set_transform()'s MouseTransformInfo argPhilippe Mathieu-Daudé2-3/+2
2023-01-05Merge tag 'mem-2023-01-02' of https://github.com/davidhildenbrand/qemu into s...Peter Maydell1-9/+9
2023-01-05hw/timer/imx_epit: fix compare timer handlingAxel Heider1-72/+112
2023-01-05hw/timer/imx_epit: remove explicit fields cnt and freqAxel Heider1-45/+28
2023-01-05hw/timer/imx_epit: factor out register write handlersAxel Heider1-94/+113
2023-01-05hw/timer/imx_epit: hard reset initializes CR with 0Axel Heider1-6/+14
2023-01-05hw/timer/imx_epit: update interrupt state on CR write accessAxel Heider1-4/+12
2023-01-05hw/timer/imx_epit: define SR_OCIFAxel Heider1-6/+6
2023-01-05hw/timer/imx_epit: cleanup CR definesAxel Heider1-2/+2
2023-01-05hw/timer/imx_epit: improve commentsAxel Heider1-4/+16
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