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2023-07-10pcie: Add a PCIe capability version helperAlex Williamson1-0/+7
Report the PCIe capability version for a device Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Robin Voetter <robin@streamhpc.com> Signed-off-by: Cédric Le Goater <clg@redhat.com>
2023-07-10s390x/ap: Wire up the device request notifier interfaceTony Krowiak1-0/+113
Let's wire up the device request notifier interface to handle device unplug requests for AP. Signed-off-by: Tony Krowiak <akrowiak@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20230530225544.280031-1-akrowiak@linux.ibm.com/ Signed-off-by: Cédric Le Goater <clg@redhat.com>
2023-07-10vfio: Fix null pointer dereference bug in vfio_bars_finalize()Avihai Horon1-1/+3
vfio_realize() has the following flow: 1. vfio_bars_prepare() -- sets VFIOBAR->size. 2. msix_early_setup(). 3. vfio_bars_register() -- allocates VFIOBAR->mr. After vfio_bars_prepare() is called msix_early_setup() can fail. If it does fail, vfio_bars_register() is never called and VFIOBAR->mr is not allocated. In this case, vfio_bars_finalize() is called as part of the error flow to free the bars' resources. However, vfio_bars_finalize() calls object_unparent() for VFIOBAR->mr after checking only VFIOBAR->size, and thus we get a null pointer dereference. Fix it by checking VFIOBAR->mr in vfio_bars_finalize(). Fixes: 89d5202edc50 ("vfio/pci: Allow relocating MSI-X MMIO") Signed-off-by: Avihai Horon <avihaih@nvidia.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Cédric Le Goater <clg@redhat.com>
2023-07-10vfio/migration: Return bool type for vfio_migration_realize()Zhenzhong Duan2-7/+11
Make vfio_migration_realize() adhere to the convention of other realize() callbacks(like qdev_realize) by returning bool instead of int. Suggested-by: Cédric Le Goater <clg@redhat.com> Suggested-by: Joao Martins <joao.m.martins@oracle.com> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Joao Martins <joao.m.martins@oracle.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Cédric Le Goater <clg@redhat.com>
2023-07-10vfio/migration: Remove print of "Migration disabled"Zhenzhong Duan1-1/+0
Property enable_migration supports [on/off/auto]. In ON mode, error pointer is passed to errp and logged. In OFF mode, we doesn't need to log "Migration disabled" as it's intentional. In AUTO mode, we should only ever see errors or warnings if the device supports migration and an error or incompatibility occurs while further probing or configuring it. Lack of support for migration shoundn't generate an error or warning. Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Joao Martins <joao.m.martins@oracle.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Cédric Le Goater <clg@redhat.com>
2023-07-10vfio/migration: Free resources when vfio_migration_realize failsZhenzhong Duan2-10/+24
When vfio_realize() succeeds, hot unplug will call vfio_exitfn() to free resources allocated in vfio_realize(); when vfio_realize() fails, vfio_exitfn() is never called and we need to free resources in vfio_realize(). In the case that vfio_migration_realize() fails, e.g: with -only-migratable & enable-migration=off, we see below: (qemu) device_add vfio-pci,host=81:11.1,id=vfio1,bus=root1,enable-migration=off 0000:81:11.1: Migration disabled Error: disallowing migration blocker (--only-migratable) for: 0000:81:11.1: Migration is disabled for VFIO device If we hotplug again we should see same log as above, but we see: (qemu) device_add vfio-pci,host=81:11.1,id=vfio1,bus=root1,enable-migration=off Error: vfio 0000:81:11.1: device is already attached That's because some references to VFIO device isn't released. For resources allocated in vfio_migration_realize(), free them by jumping to out_deinit path with calling a new function vfio_migration_deinit(). For resources allocated in vfio_realize(), free them by jumping to de-register path in vfio_realize(). Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Fixes: a22651053b59 ("vfio: Make vfio-pci device migration capable") Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Joao Martins <joao.m.martins@oracle.com> Signed-off-by: Cédric Le Goater <clg@redhat.com>
2023-07-10vfio/migration: Change vIOMMU blocker from global to per deviceZhenzhong Duan3-53/+6
Contrary to multiple device blocker which needs to consider already-attached devices to unblock/block dynamically, the vIOMMU migration blocker is a device specific config. Meaning it only needs to know whether the device is bypassing or not the vIOMMU (via machine property, or per pxb-pcie::bypass_iommu), and does not need the state of currently present devices. For this reason, the vIOMMU global migration blocker can be consolidated into the per-device migration blocker, allowing us to remove some unnecessary code. This change also makes vfio_mig_active() more accurate as it doesn't check for global blocker. Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Joao Martins <joao.m.martins@oracle.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Cédric Le Goater <clg@redhat.com>
2023-07-10vfio/pci: Disable INTx in vfio_realize error pathZhenzhong Duan1-0/+3
When vfio realize fails, INTx isn't disabled if it has been enabled. This may confuse host side with unhandled interrupt report. Fixes: c5478fea27ac ("vfio/pci: Respond to KVM irqchip change notifier") Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Joao Martins <joao.m.martins@oracle.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Cédric Le Goater <clg@redhat.com>
2023-07-10hw/vfio/pci-quirks: Sanitize capability pointerAlex Williamson1-2/+8
Coverity reports a tained scalar when traversing the capabilities chain (CID 1516589). In practice I've never seen a device with a chain so broken as to cause an issue, but it's also pretty easy to sanitize. Fixes: f6b30c1984f7 ("hw/vfio/pci-quirks: Support alternate offset for GPUDirect Cliques") Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Cédric Le Goater <clg@redhat.com>
2023-07-08Merge tag 'trivial-patches-20230708' of https://gitlab.com/mjt0k/qemu into ↵Richard Henderson7-36/+7
staging qemu trivial patches for 2023-07-08 # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEe3O61ovnosKJMUsicBtPaxppPlkFAmSo5UsPHG1qdEB0bHMu # bXNrLnJ1AAoJEHAbT2saaT5ZIygH/0z5heVC4CnU5sNuv8GRbXZL7sOXxvoOQf9K # dEBD0/Lzu8QL7mJBpqPuzK4FN/CNnY2nUaGGn3k7U44MrsU6g2P5ksD4Y0hUebkZ # sw+bsaqDeG0J+kZ9IN4V1iLoyGGQ53GDynisZMWY8w/hDmCkoRe5Xy2LZrXS7fgw # LVT04wlxTYG/EwXqMukBYd/S/lap8pUnzgc+VngHmX5gBF4O7qIAZV1j5WobIW6S # /OOOOBZ4YJU9Ha18H4DWrE5+ptfE2sfWAO0z+c/v3bpNTUb9bCyNIE3R3mUwg7z6 # i/96za3R9XH0ChoBWrKHtFn5wygUMGHt63JwIph0bwr73ENVlrE= # =4nBR # -----END PGP SIGNATURE----- # gpg: Signature made Sat 08 Jul 2023 05:25:47 AM BST # gpg: using RSA key 7B73BAD68BE7A2C289314B22701B4F6B1A693E59 # gpg: issuer "mjt@tls.msk.ru" # gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" [undefined] # gpg: aka "Michael Tokarev <mjt@debian.org>" [undefined] # gpg: aka "Michael Tokarev <mjt@corpit.ru>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D 4324 457C E0A0 8044 65C5 # Subkey fingerprint: 7B73 BAD6 8BE7 A2C2 8931 4B22 701B 4F6B 1A69 3E59 * tag 'trivial-patches-20230708' of https://gitlab.com/mjt0k/qemu: hw/arm/virt-acpi-build.c: Add missing header migration: unexport migrate_fd_error() migration: factor out "resume_requested" in qmp_migrate() qemu-options.hx: Fix indentation of some option descriptions vdpa: Sort vdpa_feature_bits array alphabetically vdpa: Delete duplicated VIRTIO_NET_F_RSS in vdpa_feature_bits hw: Simplify calls to pci_nic_init_nofail() trivial: man page: document display::gtk::zoom-to-fit target/avr: Fix handling of interrupts above 33. hw/riscv/virt.c: fix typo in 'aia' description Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-08hw/arm/virt-acpi-build.c: Add missing headerPeng Liang1-0/+1
virt-acpi-build.c uses warn_report. However, it doesn't include qemu/error-report.h directly, it include qemu/error-report.h via trace.h if we enable log trace backend. But if we disable the log trace backend (e.g., --enable-trace-backends=nop), then virt-acpi-build.c will not include qemu/error-report.h any more and it will lead to build errors. Include qemu/error-report.h directly in virt-acpi-build.c to avoid the errors. Fixes: 451b157041 ("acpi: Align the size to 128k") Signed-off-by: Peng Liang <tcx4c70@gmail.com> Reviewed-by: Ani Sinha <anisinha@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> (mjt: move the #include higher as suggested by Ani Sinha)
2023-07-08hw: Simplify calls to pci_nic_init_nofail()Thomas Huth5-35/+5
pci_nic_init_nofail() calls qemu_find_nic_model(), and this function sets nd->model = g_strdup(default_model) if it has not been initialized yet. So we don't have to set nd->model to the default_nic in the calling sites. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2023-07-08hw/riscv/virt.c: fix typo in 'aia' descriptionDaniel Henrique Barboza1-1/+1
Cc: qemu-trivial@nongnu.org Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2023-07-07Merge tag 'pull-ppc-20230707-1' of https://gitlab.com/danielhb/qemu into stagingRichard Henderson20-240/+568
ppc patch queue for 2023-07-07: In this last queue for 8.1 we have a lot of fixes and improvements all around: SMT support for powerNV, XIVE fixes, PPC440 cleanups, exception handling cleanups and kvm_pph.h cleanups just to name a few. Thanks everyone in the qemu-ppc community for all the contributions for the next QEMU 8.1 release. # -----BEGIN PGP SIGNATURE----- # # iIwEABYKADQWIQQX6/+ZI9AYAK8oOBk82cqW3gMxZAUCZKgihBYcZGFuaWVsaGI0 # MTNAZ21haWwuY29tAAoJEDzZypbeAzFksr0A/jrvSDSDxB5mR7bo0dNGndLXcdTo # ZGr6k6pcMpr7RDOAAQDVeaw7f8djQ4Aaelk6v1wPs5bYfNY2ElF4NsqHJFX2Cg== # =8lDs # -----END PGP SIGNATURE----- # gpg: Signature made Fri 07 Jul 2023 03:34:44 PM BST # gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164 # gpg: issuer "danielhb413@gmail.com" # gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164 * tag 'pull-ppc-20230707-1' of https://gitlab.com/danielhb/qemu: (59 commits) ppc/pnv: Add QME region for P10 target/ppc: Remove pointless checks of CONFIG_USER_ONLY in 'kvm_ppc.h' target/ppc: Restrict 'kvm_ppc.h' to sysemu in cpu_init.c target/ppc: Define TYPE_HOST_POWERPC_CPU in cpu-qom.h target/ppc: Move CPU QOM definitions to cpu-qom.h target/ppc: Reorder #ifdef'ry in kvm_ppc.h target/ppc: Have 'kvm_ppc.h' include 'sysemu/kvm.h' target/ppc: Machine check on invalid real address access on POWER9/10 tests/qtest: Add xscom tests for powernv10 machine ppc/pnv: Set P10 core xscom region size to match hardware ppc/pnv: Log all unimp warnings with similar message ppc440_pcix: Rename QOM type define abd move it to common header ppc4xx_pci: Add define for ppc4xx-host-bridge type name ppc4xx_pci: Rename QOM type name define ppc440_pcix: Stop using system io region for PCI bus ppc440_pcix: Don't use iomem for regs ppc/sam460ex: Remove address_space_mem local variable ppc440: Remove ppc460ex_pcie_init legacy init function ppc440: Add busnum property to PCIe controller model ppc440: Stop using system io region for PCIe buses ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-07ppc/pnv: Add QME region for P10Joel Stanley2-2/+79
The Quad Management Engine (QME) manages power related settings for its quad. The xscom region is separate from the quad xscoms, therefore a new region is added. The xscoms in a QME select a given core by selecting the forth nibble. Implement dummy reads for the stop state history (SSH) and special wakeup (SPWU) registers. This quietens some sxcom errors when skiboot boots on p10. Power9 does not have a QME. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-ID: <20230707071213.9924-1-joel@jms.id.au> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07igb: Remove obsolete workaround for WindowsAkihiko Odaki1-6/+1
I confirmed it works with Windows even without this workaround. It is likely to be a mistake so remove it. Fixes: 3a977deebe ("Intrdocue igb device emulation") Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-07-07e1000e: Add ICR clearing by corresponding IMS bitAkihiko Odaki2-6/+33
The datasheet does not say what happens when interrupt was asserted (ICR.INT_ASSERT=1) and auto mask is *not* active. However, section of 13.3.27 the PCIe* GbE Controllers Open Source Software Developer’s Manual, which were written for older devices, namely 631xESB/632xESB, 82563EB/82564EB, 82571EB/82572EI & 82573E/82573V/82573L, does say: > If IMS = 0b, then the ICR register is always clear-on-read. If IMS is > not 0b, but some ICR bit is set where the corresponding IMS bit is not > set, then a read does not clear the ICR register. For example, if > IMS = 10101010b and ICR = 01010101b, then a read to the ICR register > does not clear it. If IMS = 10101010b and ICR = 0101011b, then a read > to the ICR register clears it entirely (ICR.INT_ASSERTED = 1b). Linux does no longer activate auto mask since commit 0a8047ac68e50e4ccbadcfc6b6b070805b976885 and the real hardware clears ICR even in such a case so we also should do so. Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1707441 Signed-off-by: Andrew Melnychenko <andrew@daynix.com> Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-07-07hw/net: ftgmac100: Drop the small packet check in the receive pathBin Meng1-8/+0
Now that we have implemented unified short frames padding in the QEMU networking codes, the small packet check logic in the receive path is no longer needed. Suggested-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Bin Meng <bmeng@tinylab.org> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-07-07hw/net: sunhme: Remove the logic of padding short frames in the receive pathBin Meng1-11/+0
Now that we have implemented unified short frames padding in the QEMU networking codes, remove the same logic in the NIC codes. Signed-off-by: Bin Meng <bmeng@tinylab.org> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-07-07hw/net: sungem: Remove the logic of padding short frames in the receive pathBin Meng1-14/+0
Now that we have implemented unified short frames padding in the QEMU networking codes, remove the same logic in the NIC codes. Signed-off-by: Bin Meng <bmeng@tinylab.org> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-07-07hw/net: rtl8139: Remove the logic of padding short frames in the receive pathBin Meng1-12/+0
Now that we have implemented unified short frames padding in the QEMU networking codes, remove the same logic in the NIC codes. Signed-off-by: Bin Meng <bmeng@tinylab.org> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-07-07hw/net: pcnet: Remove the logic of padding short frames in the receive pathBin Meng1-9/+0
Now that we have implemented unified short frames padding in the QEMU networking codes, remove the same logic in the NIC codes. Signed-off-by: Bin Meng <bmeng@tinylab.org> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-07-07hw/net: ne2000: Remove the logic of padding short frames in the receive pathBin Meng1-12/+0
Now that we have implemented unified short frames padding in the QEMU networking codes, remove the same logic in the NIC codes. Signed-off-by: Bin Meng <bmeng@tinylab.org> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-07-07hw/net: i82596: Remove the logic of padding short frames in the receive pathBin Meng1-18/+0
Now that we have implemented unified short frames padding in the QEMU networking codes, remove the same logic in the NIC codes. Signed-off-by: Bin Meng <bmeng@tinylab.org> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-07-07hw/net: vmxnet3: Remove the logic of padding short frames in the receive pathBin Meng1-10/+0
Now that we have implemented unified short frames padding in the QEMU networking codes, remove the same logic in the NIC codes. This actually reverts commit 40a87c6c9b11ef9c14e0301f76abf0eb2582f08e. Signed-off-by: Bin Meng <bmeng@tinylab.org> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-07-07hw/net: e1000: Remove the logic of padding short frames in the receive pathBin Meng1-10/+1
Now that we have implemented unified short frames padding in the QEMU networking codes, remove the same logic in the NIC codes. This actually reverts commit 78aeb23eded2d0b765bf9145c71f80025b568acd. Signed-off-by: Bin Meng <bmeng@tinylab.org> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-07-07virtio-net: correctly report maximum tx_queue_size valueLaurent Vivier1-2/+2
Maximum value for tx_queue_size depends on the backend type. 1024 for vDPA/vhost-user, 256 for all the others. The value is returned by virtio_net_max_tx_queue_size() to set the parameter: n->net_conf.tx_queue_size = MIN(virtio_net_max_tx_queue_size(n), n->net_conf.tx_queue_size); But the parameter checking uses VIRTQUEUE_MAX_SIZE (1024). So the parameter is silently ignored and ethtool reports a different value than the one provided by the user. ... -netdev tap,... -device virtio-net,tx_queue_size=1024 # ethtool -g enp0s2 Ring parameters for enp0s2: Pre-set maximums: RX: 256 RX Mini: n/a RX Jumbo: n/a TX: 256 Current hardware settings: RX: 256 RX Mini: n/a RX Jumbo: n/a TX: 256 ... -netdev vhost-user,... -device virtio-net,tx_queue_size=2048 Invalid tx_queue_size (= 2048), must be a power of 2 between 256 and 1024 With this patch the correct maximum value is checked and displayed. For vDPA/vhost-user: Invalid tx_queue_size (= 2048), must be a power of 2 between 256 and 1024 For all the others: Invalid tx_queue_size (= 512), must be a power of 2 between 256 and 256 Fixes: 2eef278b9e63 ("virtio-net: fix tx queue size for !vhost-user") Cc: mst@redhat.com Cc: qemu-stable@nongnu.org Signed-off-by: Laurent Vivier <lvivier@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2023-07-07ppc/pnv: Set P10 core xscom region size to match hardwareNicholas Piggin1-2/+4
The P10 core xscom memory regions overlap because the size is wrong. The P10 core+L2 xscom region size is allocated as 0x1000 (with some unused ranges). "EC" is used as a closer match, as "EX" includes L3 which has a disjoint xscom range that would require a different region if it were implemented. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Message-ID: <20230706053923.115003-2-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc/pnv: Log all unimp warnings with similar messageJoel Stanley1-16/+18
Add the function name so there's an indication as to where the message is coming from. Change all prints to use the offset instead of the address. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230706024528.40065-1-joel@jms.id.au> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc440_pcix: Rename QOM type define abd move it to common headerBALATON Zoltan2-6/+5
Rename TYPE_PPC440_PCIX_HOST_BRIDGE to better match its string value, move it to common header and use it also in sam460ex to replace hard coded type name. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-ID: <1a1c3fe4b120f345d1005ad7ceca4500783691f7.1688641673.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc4xx_pci: Add define for ppc4xx-host-bridge type nameBALATON Zoltan2-3/+4
Add a QOM type name define for ppc4xx-host-bridge in the common header and replace direct use of the string name with the constant. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-ID: <f6e2956b3a09ee481b970ef7873b374c846ba0a8.1688641673.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc4xx_pci: Rename QOM type name defineBALATON Zoltan2-5/+4
Rename the TYPE_PPC4xx_PCI_HOST_BRIDGE define and its string value to match each other and other similar types and to avoid confusion with "ppc4xx-host-bridge" type defined in same file. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-ID: <c59c28ef440633dbd1de0bda0a93b7862ef91104.1688641673.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc440_pcix: Stop using system io region for PCI busBALATON Zoltan2-8/+7
Reduce the iomem region to 64K and use it for the PCI io space and map it directly from the board without an intermediate alias that is not really needed. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <f4ad9af42197a92dd1d0b56c21316dbdad240ee4.1688641673.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc440_pcix: Don't use iomem for regsBALATON Zoltan1-3/+4
The iomem memory region is better used for the PCI IO space but currently used for registers. Stop using it for that to allow this to be cleaned up in the next patch. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <3def68f200edd4540393d6b3b03baabe15d649f2.1688586835.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc/sam460ex: Remove address_space_mem local variableBALATON Zoltan1-4/+4
Some places already use get_system_memory() directly so replace the remaining uses and drop the local variable. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-ID: <d134d64f13258d1f157b445fedb1e86cf3abb606.1688586835.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc440: Remove ppc460ex_pcie_init legacy init functionBALATON Zoltan3-23/+16
After previous changes we can now remove the legacy init function and move the device creation to board code. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <29aafeea9f1c871c739600a7b093c5456e8a1dc8.1688586835.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc440: Add busnum property to PCIe controller modelBALATON Zoltan1-14/+11
Instead of guessing controller number from dcrn_base add a property so the device does not need knowledge about where it is used. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <fdb84344025e00fadf74d0be95665fcb0ac1e039.1688586835.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc440: Stop using system io region for PCIe busesBALATON Zoltan1-3/+6
Add separate memory regions for the mem and io spaces of the PCIe bus to avoid different buses using the same system io region. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <b631c3a61729eee2166d899b8888164ebeb71574.1688586835.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc440: Rename local variable in dcr_read_pcie()BALATON Zoltan1-25/+25
Rename local variable storing state struct in dcr_read_pcie() for brevity and consistency with other functions. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <7b6f0033ada74075fc094b1397deb406e1a05741.1688586835.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc440: Rename parent field of PPC460EXPCIEState to match code styleBALATON Zoltan1-1/+1
QOM prefers to call the parent field parent_obj, change PPC460EXPCIEState ro match that convention. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <6995f28215d2a489a661b7d91a1783048829d467.1688586835.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc440: Add a macro to shorten PCIe controller DCR registrationBALATON Zoltan1-48/+28
It is shorter and more readable to wrap the complex call to ppc_dcr_register() in a macro than to repeat it several times. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <4dec5ef8115791dc67253afdff9a703eb816a2a8.1688586835.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc440: Add cpu link property to PCIe controller modelBALATON Zoltan1-52/+62
The PCIe controller model uses PPC DCRs but cannot be modeled with TYPE_PPC4xx_DCR_DEVICE as it derives from TYPE_PCIE_HOST_BRIDGE. Add a cpu link property to it similar to other DCR devices to allow registering DCRs from the device model. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <a79796654deaa81a6a1c71efc874e4d88c4cafd4.1688586835.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc440: Change ppc460ex_pcie_init() parameter typeBALATON Zoltan3-5/+6
Change parameter of ppc460ex_pcie_init() from env to cpu to allow further refactoring. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <1695d7cc1a9f1070ab498c078916e2389d6e9469.1688586835.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc/pnv: SMT support for powernvNicholas Piggin2-8/+17
Set the TIR default value with the SMT thread index, and place some standard limits on SMT configurations. Now powernv is able to boot skiboot and Linux with a SMT topology, including booting a KVM guest. There are several SPRs and other features (e.g., broadcast msgsnd) that are not implemented, but not used by OPAL or Linux and can be added incrementally. Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <20230705120631.27670-4-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07target/ppc: Add LPAR-per-core vs per-thread mode flagNicholas Piggin1-0/+2
The Power ISA has the concept of sub-processors: Hardware is allowed to sub-divide a multi-threaded processor into "sub-processors" that appear to privileged programs as multi-threaded processors with fewer threads. POWER9 and POWER10 have two modes, either every thread is a sub-processor or all threads appear as one multi-threaded processor. In the user manuals these are known as "LPAR per thread" / "Thread LPAR", and "LPAR per core" / "1 LPAR", respectively. The practical difference is: in thread LPAR mode, non-hypervisor SPRs are not shared between threads and msgsndp can not be used to message siblings. In 1 LPAR mode, some SPRs are shared and msgsndp is usable. Thrad LPAR allows multiple partitions to run concurrently on the same core, and is a requirement for KVM to run on POWER9/10 (which does not gang-schedule an LPAR on all threads of a core like POWER8 KVM). Traditionally, SMT in PAPR environments including PowerVM and the pseries QEMU machine with KVM acceleration behaves as in 1 LPAR mode. In OPAL systems, Thread LPAR is used. When adding SMT to the powernv machine, it is therefore preferable to emulate Thread LPAR. To account for this difference between pseries and powernv, an LPAR mode flag is added such that SPRs can be implemented as per-LPAR shared, and that becomes either per-thread or per-core depending on the flag. Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <20230705120631.27670-2-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07pnv/xive2: Always pass a presenter object when accessing the TIMAFrederic Barrat1-2/+4
The low-level functions to access the TIMA take a presenter object as a first argument. When accessing the TIMA from the IC BAR, i.e. indirect calls, we currently pass a NULL pointer for the presenter argument. While it appears ok with the current usage, it's dangerous. And it's pretty easy to figure out the presenter in that context, so this patch fixes it. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-ID: <20230705081400.218408-1-fbarrat@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07pnv/xive: Print CPU target in all TIMA tracesFrederic Barrat2-4/+4
Add the CPU target in the trace when reading/writing the TIMA space. It was already done for other TIMA ops (notify, accept, ...), only missing for those 2. Useful for debug and even more now that we experiment with SMT. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-ID: <20230705110039.231148-1-fbarrat@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc/pegasos2: Add support for -initrd command line optionBALATON Zoltan1-1/+31
This also changes type of sz local variable to ssize_t because it is used to store return value of load_elf() and load_image_targphys() that return ssize_t. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-ID: <20230704181920.27B58746335@zero.eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07pnv/xive: Allow mmio operations of any size on the ESB CI pagesFrederic Barrat2-6/+6
We currently only allow 64-bit operations on the ESB CI pages. There's no real reason for that limitation, skiboot/linux didn't need more. However the hardware supports any size, so this patch relaxes that restriction. It impacts both the ESB pages for "normal" interrupts as well as the ESB pages for escalation interrupts defined for the ENDs. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-ID: <20230704144848.164287-1-fbarrat@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-07-07ppc/pnv: Return zero for core thread state xscomJoel Stanley1-0/+10
Firmware now warns if booting in LPAR per core mode (PPC bit 62). So this warning doesn't trigger, report the core thread state is 0. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-ID: <20230704054204.168547-6-joel@jms.id.au> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
generated by cgit v1.1 at 2025-02-01 10:06:02 +0000