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2021-10-30hw/timer/sh_timer: Rename sh_timer_state to SHTimerStateBALATON Zoltan1-9/+9
2021-10-30hw/intc/sh_intc: Remove unneeded local variable initialisersBALATON Zoltan1-11/+10
2021-10-30hw/intc/sh_intc: Simplify allocating sources arrayBALATON Zoltan1-11/+4
2021-10-30hw/intc/sh_intc: Avoid using continue in loopsBALATON Zoltan1-24/+20
2021-10-30hw/intc/sh_intc: Replace abort() with g_assert_not_reached()BALATON Zoltan1-5/+3
2021-10-30hw/intc/sh_intc: Inline and drop sh_intc_source() functionBALATON Zoltan2-34/+24
2021-10-30hw/intc/sh_intc: Use array index instead of pointer arithmeticsBALATON Zoltan1-14/+14
2021-10-30hw/intc/sh_intc: Remove excessive parenthesisBALATON Zoltan1-4/+5
2021-10-30hw/intc/sh_intc: Move sh_intc_register() closer to its only userBALATON Zoltan1-30/+30
2021-10-30hw/intc/sh_intc: Drop another useless macroBALATON Zoltan1-11/+4
2021-10-30hw/intc/sh_intc: Rename iomem regionBALATON Zoltan1-7/+4
2021-10-30hw/intc/sh_intc: Turn some defines into an enumBALATON Zoltan1-24/+18
2021-10-30hw/intc/sh_intc: Use existing macro instead of local oneBALATON Zoltan1-7/+5
2021-10-30hw/char/sh_serial: Add device id to trace outputBALATON Zoltan2-4/+6
2021-10-30hw/char/sh_serial: QOM-ifyBALATON Zoltan2-54/+100
2021-10-30hw/char/sh_serial: Split off sh_serial_reset() from sh_serial_init()BALATON Zoltan1-12/+17
2021-10-30hw/char/sh_serial: Embed QEMUTimer in state structBALATON Zoltan1-5/+5
2021-10-30hw/char/sh_serial: Rename type sh_serial_state to SHSerialStateBALATON Zoltan1-13/+11
2021-10-30hw/char/sh_serial: Do not abort on invalid accessBALATON Zoltan1-9/+10
2021-10-30hw/sh4/r2d: Use error_report instead of fprintf to stderrBALATON Zoltan1-2/+3
2021-10-30hw/sh4: Change debug printfs to tracesBALATON Zoltan9-92/+51
2021-10-30hw/sh4: Fix typos in a commentBALATON Zoltan1-1/+1
2021-10-30hw/sh4: Coding style: Remove unnecessary castsBALATON Zoltan1-2/+2
2021-10-30hw/sh4: Coding style: Add missing bracesBALATON Zoltan6-81/+118
2021-10-30hw/sh4: Coding style: White space fixesBALATON Zoltan9-85/+99
2021-10-30hw/sh4: Coding style: Fix multi-line commentsBALATON Zoltan7-278/+286
2021-10-30hw/sh4: Coding style: Remove tabsBALATON Zoltan5-1253/+1252
2021-10-28hw/riscv: opentitan: Fixup the PLIC context addressesAlistair Francis1-2/+2
2021-10-28hw/riscv: virt: Use the PLIC config helper functionAlistair Francis1-19/+1
2021-10-28hw/riscv: microchip_pfsoc: Use the PLIC config helper functionAlistair Francis1-13/+1
2021-10-28hw/riscv: sifive_u: Use the PLIC config helper functionAlistair Francis1-13/+1
2021-10-28hw/riscv: boot: Add a PLIC config string functionAlistair Francis1-0/+25
2021-10-28hw/riscv: virt: Don't use a macro for the PLIC configurationAlistair Francis1-1/+1
2021-10-279pfs: use P9Array in v9fs_walk()Christian Schoenebeck1-12/+5
2021-10-279pfs: make V9fsPath usable via P9Array APIChristian Schoenebeck1-0/+2
2021-10-279pfs: simplify blksize_to_iounit()Christian Schoenebeck1-2/+1
2021-10-279pfs: deduplicate iounit codeChristian Schoenebeck1-21/+20
2021-10-279pfs: fix wrong I/O block size in RgetattrChristian Schoenebeck1-1/+20
2021-10-23Merge remote-tracking branch 'remotes/vivier/tags/trivial-branch-for-6.2-pull...Richard Henderson3-14/+33
2021-10-23hw/nvram: Fix Memory Leak in Xilinx ZynqMP eFuse deviceTong Ho1-6/+12
2021-10-23hw/nvram: Fix Memory Leak in Xilinx Versal eFuse deviceTong Ho1-5/+15
2021-10-23hw/nvram: Fix Memory Leak in Xilinx eFuse QOMTong Ho1-3/+6
2021-10-22Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-apply-202...Richard Henderson11-396/+113
2021-10-22Merge remote-tracking branch 'remotes/clg/tags/pull-aspeed-20211022' into sta...Richard Henderson4-4/+90
2021-10-22Merge remote-tracking branch 'remotes/vivier-m68k/tags/q800-pull-request' int...Richard Henderson3-5/+188
2021-10-22hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_idBin Meng1-4/+2
2021-10-22hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_idBin Meng1-4/+2
2021-10-22hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_idBin Meng1-4/+12
2021-10-22hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_idBin Meng1-4/+2
2021-10-22hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_idBin Meng1-4/+12
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