riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-09-14	hw/arm/npcm7xx: add board setup stub for CPU and UART clocks	Havard Skinnemoen	1	-0/+32
2020-09-14	hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj	Havard Skinnemoen	1	-0/+20
2020-09-14	hw/ssi: NPCM7xx Flash Interface Unit device model	Havard Skinnemoen	5	-0/+643
2020-09-14	hw/mem: Stubbed out NPCM7xx Memory Controller model	Havard Skinnemoen	3	-0/+91
2020-09-14	hw/nvram: NPCM7xx OTP device model	Havard Skinnemoen	3	-0/+470
2020-09-14	hw/arm: Load -bios image as a boot ROM for npcm7xx	Havard Skinnemoen	1	-0/+32
2020-09-14	hw/arm: Add two NPCM7xx-based machines	Havard Skinnemoen	2	-1/+146
2020-09-14	hw/arm: Add NPCM730 and NPCM750 SoC models	Havard Skinnemoen	3	-0/+413
2020-09-14	hw/timer: Add NPCM7xx Timer device model	Havard Skinnemoen	3	-0/+549
2020-09-14	hw/misc: Add NPCM7xx Clock Controller device model	Havard Skinnemoen	3	-0/+271
2020-09-14	hw/misc: Add NPCM7xx System Global Control Registers device model	Havard Skinnemoen	4	-0/+279
2020-09-14	hw/arm: versal-virt: Correct the tx/rx GEM clocks	Edgar E. Iglesias	1	-1/+1
2020-09-14	hw/arm/mps2: New board model mps2-an500	Peter Maydell	1	-10/+55
2020-09-14	hw/arm/mps2: New board model mps2-an386	Peter Maydell	1	-5/+29
2020-09-14	hw/timer/armv7m_systick: assert that board code set system_clock_scale	Peter Maydell	1	-0/+8
2020-09-14	hw/misc/a9scu: Report unimplemented accesses with qemu_log_mask(UNIMP)	Philippe Mathieu-Daudé	1	-0/+6
2020-09-14	hw/misc/a9scu: Simplify setting MemoryRegionOps::impl fields	Philippe Mathieu-Daudé	1	-11/+5
2020-09-14	hw/misc/a9scu: Simplify setting MemoryRegionOps::valid fields	Philippe Mathieu-Daudé	1	-16/+5
2020-09-14	hw/misc/a9scu: Do not allow invalid CPU count	Philippe Mathieu-Daudé	1	-5/+13
2020-09-13	Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200...	Peter Maydell	41	-87/+1300
2020-09-12	Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-fixes-100920-...	Peter Maydell	2	-2/+2
2020-09-12	Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-5.2-pul...	Peter Maydell	13	-39/+20
2020-09-11	util/hexdump: Reorder qemu_hexdump() arguments	Philippe Mathieu-Daudé	5	-5/+5
2020-09-11	util/hexdump: Convert to take a void pointer argument	Philippe Mathieu-Daudé	4	-4/+4
2020-09-11	hw/arm/pxa2xx: Add missing fallthrough comment	Thomas Huth	1	-1/+1
2020-09-11	Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request...	Peter Maydell	368	-1669/+2391
2020-09-10	hw: hyperv: vmbus: Fix 32bit compilation	Jon Doron	1	-1/+2
2020-09-10	hw/net/e1000e: Remove duplicated write handler for FLSWDATA register	Philippe Mathieu-Daudé	1	-1/+0
2020-09-10	hw/net/e1000e: Remove overwritten read handler for STATUS register	Philippe Mathieu-Daudé	1	-1/+0
2020-09-10	hw/i386: make explicit clearing of pch_rev_id	Alex Bennée	1	-1/+1
2020-09-10	usb-host: restrict workaround to new libusb versions	Gerd Hoffmann	1	-1/+1
2020-09-09	hw/riscv: Sort the Kconfig options in alphabetical order	Bin Meng	1	-29/+29
2020-09-09	hw/riscv: Drop CONFIG_SIFIVE	Bin Meng	1	-9/+5
2020-09-09	hw/riscv: Always build riscv_hart.c	Bin Meng	2	-10/+1
2020-09-09	hw/riscv: Move sifive_test model to hw/misc	Bin Meng	6	-3/+7
2020-09-09	hw/riscv: Move sifive_uart model to hw/char	Bin Meng	7	-4/+9
2020-09-09	hw/riscv: Move riscv_htif model to hw/char	Bin Meng	6	-6/+6
2020-09-09	hw/riscv: Move sifive_plic model to hw/intc	Bin Meng	10	-6/+95
2020-09-09	hw/riscv: Move sifive_clint model to hw/intc	Bin Meng	10	-7/+15
2020-09-09	hw/riscv: Move sifive_gpio model to hw/gpio	Bin Meng	8	-10/+13
2020-09-09	hw/riscv: Move sifive_u_otp model to hw/misc	Bin Meng	5	-2/+6
2020-09-09	hw/riscv: Move sifive_u_prci model to hw/misc	Bin Meng	5	-2/+6
2020-09-09	hw/riscv: Move sifive_e_prci model to hw/misc	Bin Meng	6	-3/+9
2020-09-09	hw/riscv: sifive_u: Connect a DMA controller	Bin Meng	2	-0/+31
2020-09-09	hw/riscv: clint: Avoid using hard-coded timebase frequency	Bin Meng	6	-16/+28
2020-09-09	hw/riscv: microchip_pfsoc: Hook GPIO controllers	Bin Meng	1	-0/+14
2020-09-09	hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs	Bin Meng	1	-0/+39
2020-09-09	hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23	Bin Meng	4	-3/+7
2020-09-09	hw/net: cadence_gem: Add a new 'phy-addr' property	Bin Meng	1	-2/+3
2020-09-09	hw/riscv: microchip_pfsoc: Connect a DMA controller	Bin Meng	2	-0/+16