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Author
Files
Lines
2020-06-19
hw/riscv: sifive_u: Add a dummy DDR memory controller device
Bin Meng
1
-0
/
+4
2020-06-19
hw/riscv: sifive_u: Sort the SoC memmap table entries
Bin Meng
1
-2
/
+2
2020-06-19
hw/riscv: sifive_u: Support different boot source per MSEL pin state
Bin Meng
1
-8
/
+31
2020-06-19
hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
Bin Meng
2
-7
/
+9
2020-06-19
hw/riscv: sifive_u: Add a new property msel for MSEL pin state
Bin Meng
1
-0
/
+7
2020-06-19
hw/riscv: sifive_u: Rename serial property get/set functions to a generic name
Bin Meng
1
-6
/
+8
2020-06-19
hw/riscv: sifive_u: Add reset functionality
Bin Meng
1
-1
/
+23
2020-06-19
hw/riscv: sifive_gpio: Do not blindly trigger output IRQs
Bin Meng
1
-1
/
+3
2020-06-19
hw/riscv: sifive_u: Hook a GPIO controller
Bin Meng
1
-2
/
+41
2020-06-19
hw/riscv: sifive_gpio: Add a new 'ngpio' property
Bin Meng
1
-11
/
+19
2020-06-19
hw/riscv: sifive_gpio: Clean up the codes
Bin Meng
1
-8
/
+5
2020-06-19
hw/riscv: sifive_u: Generate device tree node for OTP
Bin Meng
1
-0
/
+11
2020-06-19
hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit
Bin Meng
1
-6
/
+1
2020-06-19
hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions
Bin Meng
1
-15
/
+14
2020-06-19
hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions
Bin Meng
1
-12
/
+12
2020-06-19
riscv/opentitan: Connect the UART device
Alistair Francis
1
-2
/
+23
2020-06-19
riscv/opentitan: Connect the PLIC device
Alistair Francis
1
-2
/
+12
2020-06-19
hw/char: Initial commit of Ibex UART
Alistair Francis
1
-0
/
+4
2020-06-19
riscv/opentitan: Fix the ROM size
Alistair Francis
1
-1
/
+2
2020-06-19
sifive_e: Support the revB machine
Alistair Francis
1
-4
/
+30
2020-06-15
qdev: Convert bus-less devices to qdev_realize() with Coccinelle
Markus Armbruster
4
-12
/
+6
2020-06-15
sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2
Markus Armbruster
3
-31
/
+19
2020-06-15
sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1
Markus Armbruster
2
-8
/
+6
2020-06-15
sysbus: Convert to sysbus_realize() etc. with Coccinelle
Markus Armbruster
5
-6
/
+6
2020-06-15
qom: Less verbose object_initialize_child()
Markus Armbruster
4
-17
/
+6
2020-06-15
qom: Tidy up a few object_initialize_child() calls
Markus Armbruster
1
-1
/
+1
2020-06-15
qdev: Convert uses of qdev_create() manually
Markus Armbruster
1
-2
/
+2
2020-06-15
qdev: Convert uses of qdev_create() with Coccinelle
Markus Armbruster
5
-10
/
+14
2020-06-15
riscv: Fix to put "riscv.hart_array" devices on sysbus
Markus Armbruster
5
-18
/
+14
2020-06-03
riscv: Initial commit of OpenTitan machine
Alistair Francis
3
-0
/
+190
2020-06-03
riscv: sifive_e: Manually define the machine
Alistair Francis
1
-11
/
+30
2020-06-03
hw/riscv: spike: Remove deprecated ISA specific machines
Alistair Francis
1
-217
/
+0
2020-06-03
hw/riscv: virt: Remove the riscv_ prefix of the machine* functions
Bin Meng
1
-10
/
+10
2020-06-03
hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions
Bin Meng
1
-12
/
+12
2020-06-03
riscv: Change the default behavior if no -bios option is specified
Bin Meng
1
-27
/
+4
2020-06-03
riscv: Suppress the error report for QEMU testing with riscv_find_firmware()
Bin Meng
1
-3
/
+11
2020-05-18
hw: Use QEMU_IS_ALIGNED() on parallel flash block size
Philippe Mathieu-Daudé
1
-1
/
+1
2020-05-15
qom: Drop parameter @errp of object_property_add() & friends
Markus Armbruster
2
-7
/
+8
2020-05-15
qom: Drop object_property_set_description() parameter @errp
Markus Armbruster
1
-3
/
+2
2020-04-29
hw/riscv/spike: Allow more than one CPUs
Anup Patel
1
-1
/
+1
2020-04-29
hw/riscv/spike: Allow loading firmware separately using -bios option
Anup Patel
1
-1
/
+23
2020-04-29
hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()
Anup Patel
3
-7
/
+10
2020-04-29
riscv: sifive_e: Support changing CPU type
Corey Wharton
1
-2
/
+3
2020-04-29
hw/riscv: Generate correct "mmu-type" for 32-bit machines
Bin Meng
3
-0
/
+12
2020-04-29
riscv/sifive_u: Add a serial property to the sifive_u machine
Bin Meng
1
-0
/
+20
2020-04-29
riscv/sifive_u: Add a serial property to the sifive_u SoC
Alistair Francis
1
-1
/
+7
2020-04-29
riscv/sifive_u: Fix up file ordering
Alistair Francis
1
-54
/
+54
2020-04-29
various: Remove suspicious '\' character outside of #define in C code
Philippe Mathieu-Daudé
1
-1
/
+1
2020-03-17
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
Peter Maydell
2
-6
/
+5
2020-03-17
hw/riscv: Let devices own the MemoryRegion they create
Philippe Mathieu-Daudé
2
-4
/
+4
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