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2020-06-19hw/riscv: sifive_u: Add a dummy DDR memory controller deviceBin Meng1-0/+4
2020-06-19hw/riscv: sifive_u: Sort the SoC memmap table entriesBin Meng1-2/+2
2020-06-19hw/riscv: sifive_u: Support different boot source per MSEL pin stateBin Meng1-8/+31
2020-06-19hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004Bin Meng2-7/+9
2020-06-19hw/riscv: sifive_u: Add a new property msel for MSEL pin stateBin Meng1-0/+7
2020-06-19hw/riscv: sifive_u: Rename serial property get/set functions to a generic nameBin Meng1-6/+8
2020-06-19hw/riscv: sifive_u: Add reset functionalityBin Meng1-1/+23
2020-06-19hw/riscv: sifive_gpio: Do not blindly trigger output IRQsBin Meng1-1/+3
2020-06-19hw/riscv: sifive_u: Hook a GPIO controllerBin Meng1-2/+41
2020-06-19hw/riscv: sifive_gpio: Add a new 'ngpio' propertyBin Meng1-11/+19
2020-06-19hw/riscv: sifive_gpio: Clean up the codesBin Meng1-8/+5
2020-06-19hw/riscv: sifive_u: Generate device tree node for OTPBin Meng1-0/+11
2020-06-19hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bitBin Meng1-6/+1
2020-06-19hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functionsBin Meng1-15/+14
2020-06-19hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functionsBin Meng1-12/+12
2020-06-19riscv/opentitan: Connect the UART deviceAlistair Francis1-2/+23
2020-06-19riscv/opentitan: Connect the PLIC deviceAlistair Francis1-2/+12
2020-06-19hw/char: Initial commit of Ibex UARTAlistair Francis1-0/+4
2020-06-19riscv/opentitan: Fix the ROM sizeAlistair Francis1-1/+2
2020-06-19sifive_e: Support the revB machineAlistair Francis1-4/+30
2020-06-15qdev: Convert bus-less devices to qdev_realize() with CoccinelleMarkus Armbruster4-12/+6
2020-06-15sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2Markus Armbruster3-31/+19
2020-06-15sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1Markus Armbruster2-8/+6
2020-06-15sysbus: Convert to sysbus_realize() etc. with CoccinelleMarkus Armbruster5-6/+6
2020-06-15qom: Less verbose object_initialize_child()Markus Armbruster4-17/+6
2020-06-15qom: Tidy up a few object_initialize_child() callsMarkus Armbruster1-1/+1
2020-06-15qdev: Convert uses of qdev_create() manuallyMarkus Armbruster1-2/+2
2020-06-15qdev: Convert uses of qdev_create() with CoccinelleMarkus Armbruster5-10/+14
2020-06-15riscv: Fix to put "riscv.hart_array" devices on sysbusMarkus Armbruster5-18/+14
2020-06-03riscv: Initial commit of OpenTitan machineAlistair Francis3-0/+190
2020-06-03riscv: sifive_e: Manually define the machineAlistair Francis1-11/+30
2020-06-03hw/riscv: spike: Remove deprecated ISA specific machinesAlistair Francis1-217/+0
2020-06-03hw/riscv: virt: Remove the riscv_ prefix of the machine* functionsBin Meng1-10/+10
2020-06-03hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functionsBin Meng1-12/+12
2020-06-03riscv: Change the default behavior if no -bios option is specifiedBin Meng1-27/+4
2020-06-03riscv: Suppress the error report for QEMU testing with riscv_find_firmware()Bin Meng1-3/+11
2020-05-18hw: Use QEMU_IS_ALIGNED() on parallel flash block sizePhilippe Mathieu-Daudé1-1/+1
2020-05-15qom: Drop parameter @errp of object_property_add() & friendsMarkus Armbruster2-7/+8
2020-05-15qom: Drop object_property_set_description() parameter @errpMarkus Armbruster1-3/+2
2020-04-29hw/riscv/spike: Allow more than one CPUsAnup Patel1-1/+1
2020-04-29hw/riscv/spike: Allow loading firmware separately using -bios optionAnup Patel1-1/+23
2020-04-29hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()Anup Patel3-7/+10
2020-04-29riscv: sifive_e: Support changing CPU typeCorey Wharton1-2/+3
2020-04-29hw/riscv: Generate correct "mmu-type" for 32-bit machinesBin Meng3-0/+12
2020-04-29riscv/sifive_u: Add a serial property to the sifive_u machineBin Meng1-0/+20
2020-04-29riscv/sifive_u: Add a serial property to the sifive_u SoCAlistair Francis1-1/+7
2020-04-29riscv/sifive_u: Fix up file orderingAlistair Francis1-54/+54
2020-04-29various: Remove suspicious '\' character outside of #define in C codePhilippe Mathieu-Daudé1-1/+1
2020-03-17Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2-6/+5
2020-03-17hw/riscv: Let devices own the MemoryRegion they createPhilippe Mathieu-Daudé2-4/+4