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2020-07-22hw/riscv: sifive_e: Correct debug block sizeBin Meng1-1/+1
2020-07-21hw: Mark nd_table[] misuse in realize methods FIXMEMarkus Armbruster1-0/+1
2020-07-13hw/riscv: Modify MROM size to end at 0x10000Bin Meng3-3/+3
2020-07-13RISC-V: Support 64 bit start addressAtish Patra2-2/+10
2020-07-13riscv: Add opensbi firmware dynamic supportAtish Patra4-15/+72
2020-07-13RISC-V: Copy the fdt in dram instead of ROMAtish Patra4-32/+63
2020-07-13riscv: Unify Qemu's reset vector code pathAtish Patra4-76/+52
2020-07-13hw/riscv: virt: Sort the SoC memmap table entriesBin Meng1-3/+3
2020-07-10error: Eliminate error_propagate() with Coccinelle, part 1Markus Armbruster3-12/+4
2020-07-10qom: Put name parameter before value / visitor parameterMarkus Armbruster5-11/+11
2020-07-10qdev: Use returned bool to check for qdev_realize() etc. failureMarkus Armbruster3-8/+4
2020-07-02hw/riscv: Allow 64 bit access to SiFive CLINTAlistair Francis1-1/+1
2020-07-02riscv: plic: Add a couple of mising sifive_plic_update callsJessica Clarke1-1/+2
2020-07-02riscv: plic: Honour source prioritiesJessica Clarke1-5/+12
2020-07-02riscv_hart: Fix riscv_harts_realize() error API violationsMarkus Armbruster1-9/+5
2020-07-02riscv/sifive_u: Fix sifive_u_soc_realize() error API violationsMarkus Armbruster1-3/+9
2020-06-19hw/riscv: sifive_u: Add a dummy DDR memory controller deviceBin Meng1-0/+4
2020-06-19hw/riscv: sifive_u: Sort the SoC memmap table entriesBin Meng1-2/+2
2020-06-19hw/riscv: sifive_u: Support different boot source per MSEL pin stateBin Meng1-8/+31
2020-06-19hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004Bin Meng2-7/+9
2020-06-19hw/riscv: sifive_u: Add a new property msel for MSEL pin stateBin Meng1-0/+7
2020-06-19hw/riscv: sifive_u: Rename serial property get/set functions to a generic nameBin Meng1-6/+8
2020-06-19hw/riscv: sifive_u: Add reset functionalityBin Meng1-1/+23
2020-06-19hw/riscv: sifive_gpio: Do not blindly trigger output IRQsBin Meng1-1/+3
2020-06-19hw/riscv: sifive_u: Hook a GPIO controllerBin Meng1-2/+41
2020-06-19hw/riscv: sifive_gpio: Add a new 'ngpio' propertyBin Meng1-11/+19
2020-06-19hw/riscv: sifive_gpio: Clean up the codesBin Meng1-8/+5
2020-06-19hw/riscv: sifive_u: Generate device tree node for OTPBin Meng1-0/+11
2020-06-19hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bitBin Meng1-6/+1
2020-06-19hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functionsBin Meng1-15/+14
2020-06-19hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functionsBin Meng1-12/+12
2020-06-19riscv/opentitan: Connect the UART deviceAlistair Francis1-2/+23
2020-06-19riscv/opentitan: Connect the PLIC deviceAlistair Francis1-2/+12
2020-06-19hw/char: Initial commit of Ibex UARTAlistair Francis1-0/+4
2020-06-19riscv/opentitan: Fix the ROM sizeAlistair Francis1-1/+2
2020-06-19sifive_e: Support the revB machineAlistair Francis1-4/+30
2020-06-15qdev: Convert bus-less devices to qdev_realize() with CoccinelleMarkus Armbruster4-12/+6
2020-06-15sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2Markus Armbruster3-31/+19
2020-06-15sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1Markus Armbruster2-8/+6
2020-06-15sysbus: Convert to sysbus_realize() etc. with CoccinelleMarkus Armbruster5-6/+6
2020-06-15qom: Less verbose object_initialize_child()Markus Armbruster4-17/+6
2020-06-15qom: Tidy up a few object_initialize_child() callsMarkus Armbruster1-1/+1
2020-06-15qdev: Convert uses of qdev_create() manuallyMarkus Armbruster1-2/+2
2020-06-15qdev: Convert uses of qdev_create() with CoccinelleMarkus Armbruster5-10/+14
2020-06-15riscv: Fix to put "riscv.hart_array" devices on sysbusMarkus Armbruster5-18/+14
2020-06-03riscv: Initial commit of OpenTitan machineAlistair Francis3-0/+190
2020-06-03riscv: sifive_e: Manually define the machineAlistair Francis1-11/+30
2020-06-03hw/riscv: spike: Remove deprecated ISA specific machinesAlistair Francis1-217/+0
2020-06-03hw/riscv: virt: Remove the riscv_ prefix of the machine* functionsBin Meng1-10/+10
2020-06-03hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functionsBin Meng1-12/+12
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