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riscv
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Author
Files
Lines
2020-10-22
hw/riscv: Load the kernel after the firmware
Alistair Francis
6
-15
/
+42
2020-10-22
hw/riscv: Add a riscv_is_32_bit() function
Alistair Francis
1
-0
/
+9
2020-10-22
hw/riscv: Return the end address of the loaded firmware
Alistair Francis
1
-11
/
+17
2020-10-22
hw/riscv: sifive_u: Allow specifying the CPU
Alistair Francis
1
-5
/
+13
2020-09-25
load_elf: Remove unused address variables from callers
BALATON Zoltan
1
-4
/
+4
2020-09-22
sifive_u: Register "start-in-flash" as class property
Eduardo Habkost
1
-8
/
+8
2020-09-22
sifive_e: Register "revb" as class property
Eduardo Habkost
1
-5
/
+6
2020-09-18
sifive_u: Rename memmap enum constants
Eduardo Habkost
1
-78
/
+78
2020-09-18
sifive_e: Rename memmap enum constants
Eduardo Habkost
1
-41
/
+41
2020-09-09
hw/riscv: Sort the Kconfig options in alphabetical order
Bin Meng
1
-29
/
+29
2020-09-09
hw/riscv: Drop CONFIG_SIFIVE
Bin Meng
1
-9
/
+5
2020-09-09
hw/riscv: Always build riscv_hart.c
Bin Meng
2
-10
/
+1
2020-09-09
hw/riscv: Move sifive_test model to hw/misc
Bin Meng
4
-102
/
+2
2020-09-09
hw/riscv: Move sifive_uart model to hw/char
Bin Meng
5
-197
/
+4
2020-09-09
hw/riscv: Move riscv_htif model to hw/char
Bin Meng
4
-266
/
+1
2020-09-09
hw/riscv: Move sifive_plic model to hw/intc
Bin Meng
7
-529
/
+9
2020-09-09
hw/riscv: Move sifive_clint model to hw/intc
Bin Meng
8
-272
/
+10
2020-09-09
hw/riscv: Move sifive_gpio model to hw/gpio
Bin Meng
5
-406
/
+2
2020-09-09
hw/riscv: Move sifive_u_otp model to hw/misc
Bin Meng
3
-192
/
+1
2020-09-09
hw/riscv: Move sifive_u_prci model to hw/misc
Bin Meng
3
-170
/
+1
2020-09-09
hw/riscv: Move sifive_e_prci model to hw/misc
Bin Meng
4
-127
/
+2
2020-09-09
hw/riscv: sifive_u: Connect a DMA controller
Bin Meng
2
-0
/
+31
2020-09-09
hw/riscv: clint: Avoid using hard-coded timebase frequency
Bin Meng
6
-16
/
+28
2020-09-09
hw/riscv: microchip_pfsoc: Hook GPIO controllers
Bin Meng
1
-0
/
+14
2020-09-09
hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
Bin Meng
1
-0
/
+39
2020-09-09
hw/riscv: microchip_pfsoc: Connect a DMA controller
Bin Meng
2
-0
/
+16
2020-09-09
hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card
Bin Meng
2
-0
/
+24
2020-09-09
hw/riscv: microchip_pfsoc: Connect 5 MMUARTs
Bin Meng
2
-0
/
+31
2020-09-09
hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board
Bin Meng
3
-0
/
+319
2020-09-09
target/riscv: cpu: Set reset vector based on the configured property value
Bin Meng
3
-0
/
+4
2020-09-09
hw/riscv: hart: Add a new 'resetvec' property
Bin Meng
1
-0
/
+3
2020-09-09
riscv: sifive_test: Allow 16-bit writes to memory region
Nathan Chancellor
1
-1
/
+1
2020-09-08
configure: do not include dependency flags in QEMU_CFLAGS and LIBS
Paolo Bonzini
1
-1
/
+1
2020-08-27
opentitan: Rename memmap enum constants
Eduardo Habkost
1
-42
/
+42
2020-08-25
hw/riscv: virt: Allow creating multiple NUMA sockets
Anup Patel
1
-227
/
+299
2020-08-25
hw/riscv: spike: Allow creating multiple NUMA sockets
Anup Patel
1
-74
/
+158
2020-08-25
hw/riscv: Add helpers for RISC-V multi-socket NUMA machines
Anup Patel
2
-0
/
+243
2020-08-25
hw/riscv: Allow creating multiple instances of PLIC
Anup Patel
4
-14
/
+16
2020-08-25
hw/riscv: Allow creating multiple instances of CLINT
Anup Patel
5
-12
/
+16
2020-08-21
hw/riscv: spike: Change the default bios to use generic platform image
Bin Meng
1
-2
/
+7
2020-08-21
hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u
Bin Meng
2
-4
/
+4
2020-08-21
hw/riscv: sifive_u: Add a dummy L2 cache controller device
Bin Meng
1
-0
/
+22
2020-08-21
meson: convert hw/arch*
Marc-André Lureau
2
-16
/
+19
2020-08-21
trace: switch position of headers to what Meson requires
Paolo Bonzini
1
-0
/
+1
2020-07-22
hw/riscv: sifive_e: Correct debug block size
Bin Meng
1
-1
/
+1
2020-07-21
hw: Mark nd_table[] misuse in realize methods FIXME
Markus Armbruster
1
-0
/
+1
2020-07-13
hw/riscv: Modify MROM size to end at 0x10000
Bin Meng
3
-3
/
+3
2020-07-13
RISC-V: Support 64 bit start address
Atish Patra
2
-2
/
+10
2020-07-13
riscv: Add opensbi firmware dynamic support
Atish Patra
4
-15
/
+72
2020-07-13
RISC-V: Copy the fdt in dram instead of ROM
Atish Patra
4
-32
/
+63
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