aboutsummaryrefslogtreecommitdiff
path: root/hw/riscv
AgeCommit message (Expand)AuthorFilesLines
2020-05-18hw: Use QEMU_IS_ALIGNED() on parallel flash block sizePhilippe Mathieu-Daudé1-1/+1
2020-05-15qom: Drop parameter @errp of object_property_add() & friendsMarkus Armbruster2-7/+8
2020-05-15qom: Drop object_property_set_description() parameter @errpMarkus Armbruster1-3/+2
2020-04-29hw/riscv/spike: Allow more than one CPUsAnup Patel1-1/+1
2020-04-29hw/riscv/spike: Allow loading firmware separately using -bios optionAnup Patel1-1/+23
2020-04-29hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()Anup Patel3-7/+10
2020-04-29riscv: sifive_e: Support changing CPU typeCorey Wharton1-2/+3
2020-04-29hw/riscv: Generate correct "mmu-type" for 32-bit machinesBin Meng3-0/+12
2020-04-29riscv/sifive_u: Add a serial property to the sifive_u machineBin Meng1-0/+20
2020-04-29riscv/sifive_u: Add a serial property to the sifive_u SoCAlistair Francis1-1/+7
2020-04-29riscv/sifive_u: Fix up file orderingAlistair Francis1-54/+54
2020-04-29various: Remove suspicious '\' character outside of #define in C codePhilippe Mathieu-Daudé1-1/+1
2020-03-17Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2-6/+5
2020-03-17hw/riscv: Let devices own the MemoryRegion they createPhilippe Mathieu-Daudé2-4/+4
2020-03-17hw/riscv: Use memory_region_init_rom() with read-only regionsPhilippe Mathieu-Daudé1-3/+2
2020-03-16riscv: sifive_u: Update BIOS_FILENAME for 32-bitBin Meng1-1/+5
2020-03-03Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf3' i...Peter Maydell5-7/+15
2020-02-28hw: Make MachineClass::is_default a boolean typePhilippe Mathieu-Daudé1-1/+1
2020-02-27hw/riscv: Provide rdtime callback for TCG in CLINT emulationAnup Patel5-7/+14
2020-02-27riscv: virt: Allow PCI address 0Bin Meng1-0/+1
2020-02-10riscv: virt: Use Goldfish RTC deviceAnup Patel2-0/+17
2020-02-10riscv/virt: Add syscon reboot and poweroff DT nodesAnup Patel1-4/+22
2020-01-29hw/core/loader: Let load_elf() populate a field with CPU-specific flagsAleksandar Markovic1-2/+2
2020-01-27Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell4-4/+4
2020-01-24qdev: set properties with device_class_set_props()Marc-André Lureau4-4/+4
2020-01-16riscv/sifive_u: fix a memory leak in soc_realize()Pan Nengyuan1-0/+1
2020-01-08chardev: Use QEMUChrEvent enum in IOEventHandler typedefPhilippe Mathieu-Daudé2-2/+2
2019-11-25hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()Zhuang, Siwei (Data61, Kensington NSW)5-9/+12
2019-11-25RISC-V: virt: This is a "sifive,test1" test finisherPalmer Dabbelt1-1/+4
2019-11-14riscv/virt: Increase flash sizeAlistair Francis1-1/+1
2019-10-28riscv/boot: Fix possible memory leakAlistair Francis1-7/+4
2019-10-28riscv/virt: Jump to pflash if specifiedAlistair Francis1-1/+10
2019-10-28riscv/virt: Add the PFlash CFI01 deviceAlistair Francis2-0/+87
2019-10-28riscv/virt: Manually define the machineAlistair Francis1-6/+24
2019-10-28riscv/sifive_u: Add the start-in-flash propertyAlistair Francis1-1/+29
2019-10-28riscv/sifive_u: Manually define the machineAlistair Francis1-13/+31
2019-10-28riscv/sifive_u: Add QSPI memory regionAlistair Francis1-0/+8
2019-10-28riscv/sifive_u: Add L2-LIM cache memoryAlistair Francis1-0/+16
2019-10-28riscv: sifive_u: Add ethernet0 to the aliases nodeBin Meng1-1/+4
2019-10-28riscv: hw: Drop "clock-frequency" property of cpu nodesBin Meng3-6/+0
2019-09-17riscv: sifive_u: Update model and compatible strings in device treeBin Meng1-2/+3
2019-09-17riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernetBin Meng1-23/+1
2019-09-17riscv: sifive_u: Fix broken GEM supportBin Meng2-4/+21
2019-09-17riscv: sifive_u: Instantiate OTP memory with a serial numberBin Meng1-0/+9
2019-09-17riscv: sifive: Implement a model for SiFive FU540 OTPBin Meng2-0/+192
2019-09-17riscv: sifive_u: Change UART node name in device treeBin Meng1-1/+1
2019-09-17riscv: sifive_u: Update UART base addresses and IRQsBin Meng1-2/+2
2019-09-17riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodesBin Meng1-3/+4
2019-09-17riscv: sifive_u: Add PRCI block to the SoCBin Meng1-1/+23
2019-09-17riscv: sifive_u: Generate hfclk and rtcclk nodesBin Meng1-0/+23