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path: root/hw/riscv/virt.c
AgeCommit message (Expand)AuthorFilesLines
2021-06-08hw/riscv: Use macros for BIOS image namesBin Meng1-4/+2
2021-06-08hw/riscv: Support the official PLIC DT bindingsBin Meng1-1/+5
2021-06-08hw/riscv: Support the official CLINT DT bindingsBin Meng1-1/+5
2021-06-08hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helperBin Meng1-2/+5
2021-05-02hw: Do not include qemu/log.h if it is not necessaryThomas Huth1-1/+0
2021-03-22hw/riscv: allow ramfb on virtAsherah Connor1-0/+3
2021-03-22hw/riscv: Add fw_cfg support to virtAsherah Connor1-0/+30
2021-03-10hw/riscv: migrate fdt field to generic MachineStateAlex Bennée1-10/+10
2021-03-04hw/riscv: virt: Map high mmio for PCIeBin Meng1-2/+33
2021-03-04hw/riscv: virt: Limit RAM size in a 32-bit systemBin Meng1-0/+10
2021-03-04hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()Bin Meng1-7/+7
2021-03-04hw/riscv: Drop 'struct MemmapEntry'Bin Meng1-6/+3
2021-01-16riscv: Pass RISCVHartArrayState by pointerAlistair Francis1-4/+4
2020-12-17hw/riscv: Use the CPU to determine if 32-bitAlistair Francis1-4/+5
2020-12-17hw/riscv: virt: Remove compile time XLEN checksAlistair Francis1-15/+17
2020-12-17hw/riscv: boot: Remove compile time XLEN checksAlistair Francis1-1/+1
2020-12-17riscv: virt: Remove target macro conditionalsAlistair Francis1-1/+1
2020-12-15vl: make qemu_get_machine_opts staticPaolo Bonzini1-4/+2
2020-11-03hw/riscv: virt: Allow passing custom DTBAnup Patel1-7/+20
2020-10-22hw/riscv: Load the kernel after the firmwareAlistair Francis1-3/+8
2020-09-09hw/riscv: Move sifive_test model to hw/miscBin Meng1-1/+1
2020-09-09hw/riscv: Move sifive_plic model to hw/intcBin Meng1-1/+1
2020-09-09hw/riscv: Move sifive_clint model to hw/intcBin Meng1-1/+1
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng1-1/+2
2020-08-25hw/riscv: virt: Allow creating multiple NUMA socketsAnup Patel1-227/+299
2020-08-25hw/riscv: Allow creating multiple instances of PLICAnup Patel1-1/+1
2020-08-25hw/riscv: Allow creating multiple instances of CLINTAnup Patel1-1/+1
2020-08-21hw/riscv: Use pre-built bios image of generic platform for virt & sifive_uBin Meng1-2/+2
2020-07-13hw/riscv: Modify MROM size to end at 0x10000Bin Meng1-1/+1
2020-07-13riscv: Add opensbi firmware dynamic supportAtish Patra1-3/+9
2020-07-13RISC-V: Copy the fdt in dram instead of ROMAtish Patra1-1/+6
2020-07-13riscv: Unify Qemu's reset vector code pathAtish Patra1-37/+3
2020-07-13hw/riscv: virt: Sort the SoC memmap table entriesBin Meng1-3/+3
2020-07-10qom: Put name parameter before value / visitor parameterMarkus Armbruster1-2/+2
2020-06-15sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1Markus Armbruster1-4/+3
2020-06-15sysbus: Convert to sysbus_realize() etc. with CoccinelleMarkus Armbruster1-2/+2
2020-06-15qdev: Convert uses of qdev_create() manuallyMarkus Armbruster1-2/+2
2020-06-15qdev: Convert uses of qdev_create() with CoccinelleMarkus Armbruster1-2/+2
2020-06-15riscv: Fix to put "riscv.hart_array" devices on sysbusMarkus Armbruster1-2/+2
2020-06-03hw/riscv: virt: Remove the riscv_ prefix of the machine* functionsBin Meng1-10/+10
2020-05-18hw: Use QEMU_IS_ALIGNED() on parallel flash block sizePhilippe Mathieu-Daudé1-1/+1
2020-05-15qom: Drop parameter @errp of object_property_add() & friendsMarkus Armbruster1-3/+2
2020-04-29hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()Anup Patel1-1/+1
2020-04-29hw/riscv: Generate correct "mmu-type" for 32-bit machinesBin Meng1-0/+4
2020-02-27hw/riscv: Provide rdtime callback for TCG in CLINT emulationAnup Patel1-1/+1
2020-02-27riscv: virt: Allow PCI address 0Bin Meng1-0/+1
2020-02-10riscv: virt: Use Goldfish RTC deviceAnup Patel1-0/+16
2020-02-10riscv/virt: Add syscon reboot and poweroff DT nodesAnup Patel1-4/+22
2019-11-25hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()Zhuang, Siwei (Data61, Kensington NSW)1-1/+2
2019-11-25RISC-V: virt: This is a "sifive,test1" test finisherPalmer Dabbelt1-1/+4
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