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path: root/hw/riscv/sifive_u.c
AgeCommit message (Expand)AuthorFilesLines
2020-09-09hw/riscv: Move sifive_uart model to hw/charBin Meng1-1/+1
2020-09-09hw/riscv: Move sifive_plic model to hw/intcBin Meng1-1/+1
2020-09-09hw/riscv: Move sifive_clint model to hw/intcBin Meng1-1/+1
2020-09-09hw/riscv: sifive_u: Connect a DMA controllerBin Meng1-0/+30
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng1-1/+2
2020-09-09target/riscv: cpu: Set reset vector based on the configured property valueBin Meng1-0/+2
2020-08-25hw/riscv: Allow creating multiple instances of PLICAnup Patel1-1/+1
2020-08-25hw/riscv: Allow creating multiple instances of CLINTAnup Patel1-1/+1
2020-08-21hw/riscv: Use pre-built bios image of generic platform for virt & sifive_uBin Meng1-2/+2
2020-08-21hw/riscv: sifive_u: Add a dummy L2 cache controller deviceBin Meng1-0/+22
2020-07-21hw: Mark nd_table[] misuse in realize methods FIXMEMarkus Armbruster1-0/+1
2020-07-13hw/riscv: Modify MROM size to end at 0x10000Bin Meng1-1/+1
2020-07-13RISC-V: Support 64 bit start addressAtish Patra1-1/+5
2020-07-13riscv: Add opensbi firmware dynamic supportAtish Patra1-5/+15
2020-07-13RISC-V: Copy the fdt in dram instead of ROMAtish Patra1-15/+13
2020-07-13riscv: Unify Qemu's reset vector code pathAtish Patra1-1/+0
2020-07-10error: Eliminate error_propagate() with Coccinelle, part 1Markus Armbruster1-3/+1
2020-07-10qom: Put name parameter before value / visitor parameterMarkus Armbruster1-3/+3
2020-07-10qdev: Use returned bool to check for qdev_realize() etc. failureMarkus Armbruster1-2/+1
2020-07-02riscv/sifive_u: Fix sifive_u_soc_realize() error API violationsMarkus Armbruster1-3/+9
2020-06-19hw/riscv: sifive_u: Add a dummy DDR memory controller deviceBin Meng1-0/+4
2020-06-19hw/riscv: sifive_u: Sort the SoC memmap table entriesBin Meng1-2/+2
2020-06-19hw/riscv: sifive_u: Support different boot source per MSEL pin stateBin Meng1-8/+31
2020-06-19hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004Bin Meng1-3/+3
2020-06-19hw/riscv: sifive_u: Add a new property msel for MSEL pin stateBin Meng1-0/+7
2020-06-19hw/riscv: sifive_u: Rename serial property get/set functions to a generic nameBin Meng1-6/+8
2020-06-19hw/riscv: sifive_u: Add reset functionalityBin Meng1-1/+23
2020-06-19hw/riscv: sifive_u: Hook a GPIO controllerBin Meng1-2/+41
2020-06-19hw/riscv: sifive_u: Generate device tree node for OTPBin Meng1-0/+11
2020-06-19hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bitBin Meng1-6/+1
2020-06-15qdev: Convert bus-less devices to qdev_realize() with CoccinelleMarkus Armbruster1-6/+3
2020-06-15sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2Markus Armbruster1-19/+12
2020-06-15qom: Less verbose object_initialize_child()Markus Armbruster1-9/+3
2020-06-15riscv: Fix to put "riscv.hart_array" devices on sysbusMarkus Armbruster1-8/+6
2020-06-03hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functionsBin Meng1-12/+12
2020-05-15qom: Drop parameter @errp of object_property_add() & friendsMarkus Armbruster1-4/+6
2020-05-15qom: Drop object_property_set_description() parameter @errpMarkus Armbruster1-3/+2
2020-04-29hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()Anup Patel1-1/+1
2020-04-29hw/riscv: Generate correct "mmu-type" for 32-bit machinesBin Meng1-0/+4
2020-04-29riscv/sifive_u: Add a serial property to the sifive_u machineBin Meng1-0/+20
2020-04-29riscv/sifive_u: Add a serial property to the sifive_u SoCAlistair Francis1-1/+7
2020-04-29riscv/sifive_u: Fix up file orderingAlistair Francis1-54/+54
2020-04-29various: Remove suspicious '\' character outside of #define in C codePhilippe Mathieu-Daudé1-1/+1
2020-03-17Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell1-1/+1
2020-03-17hw/riscv: Let devices own the MemoryRegion they createPhilippe Mathieu-Daudé1-1/+1
2020-03-16riscv: sifive_u: Update BIOS_FILENAME for 32-bitBin Meng1-1/+5
2020-02-27hw/riscv: Provide rdtime callback for TCG in CLINT emulationAnup Patel1-1/+1
2020-01-16riscv/sifive_u: fix a memory leak in soc_realize()Pan Nengyuan1-0/+1
2019-11-25hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()Zhuang, Siwei (Data61, Kensington NSW)1-1/+2
2019-10-28riscv/sifive_u: Add the start-in-flash propertyAlistair Francis1-1/+29
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