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path: root/hw/riscv/sifive_u.c
AgeCommit message (Expand)AuthorFilesLines
2021-09-21hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO linesAlistair Francis1-1/+1
2021-08-26arch_init.h: Don't include arch_init.h unnecessarilyPeter Maydell1-1/+0
2021-07-15hw/riscv: sifive_u: Make sure firmware info is 8-byte alignedBin Meng1-2/+3
2021-07-15hw/riscv: sifive_u: Correct the CLINT timebase frequencyBin Meng1-2/+5
2021-06-08hw/riscv: Use macros for BIOS image namesBin Meng1-4/+2
2021-06-08hw/riscv: Support the official PLIC DT bindingsBin Meng1-1/+5
2021-06-08hw/riscv: Support the official CLINT DT bindingsBin Meng1-1/+5
2021-06-08hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helperBin Meng1-3/+3
2021-05-02hw: Do not include qemu/log.h if it is not necessaryThomas Huth1-1/+0
2021-03-04hw/riscv: Drop 'struct MemmapEntry'Bin Meng1-7/+4
2021-03-04hw/riscv: sifive_u: Add QSPI2 controller and connect an SD cardBin Meng1-2/+41
2021-03-04hw/riscv: sifive_u: Add QSPI0 controller and connect a flashBin Meng1-0/+52
2021-01-16riscv: Pass RISCVHartArrayState by pointerAlistair Francis1-5/+5
2021-01-16hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_typeBin Meng1-5/+1
2020-12-17hw/riscv: Use the CPU to determine if 32-bitAlistair Francis1-5/+5
2020-12-17hw/riscv: sifive_u: Remove compile time XLEN checksAlistair Francis1-25/+30
2020-12-17hw/riscv: boot: Remove compile time XLEN checksAlistair Francis1-1/+1
2020-12-17hw/riscv: sifive_u: Add UART1 DT node in the generated DTBAnup Patel1-0/+15
2020-12-15vl: make qemu_get_machine_opts staticPaolo Bonzini1-4/+2
2020-11-03hw/riscv: sifive_u: Allow passing custom DTBAnup Patel1-8/+20
2020-10-22hw/riscv: Load the kernel after the firmwareAlistair Francis1-2/+8
2020-10-22hw/riscv: sifive_u: Allow specifying the CPUAlistair Francis1-5/+13
2020-09-22sifive_u: Register "start-in-flash" as class propertyEduardo Habkost1-8/+8
2020-09-18sifive_u: Rename memmap enum constantsEduardo Habkost1-78/+78
2020-09-09hw/riscv: Move sifive_uart model to hw/charBin Meng1-1/+1
2020-09-09hw/riscv: Move sifive_plic model to hw/intcBin Meng1-1/+1
2020-09-09hw/riscv: Move sifive_clint model to hw/intcBin Meng1-1/+1
2020-09-09hw/riscv: sifive_u: Connect a DMA controllerBin Meng1-0/+30
2020-09-09hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng1-1/+2
2020-09-09target/riscv: cpu: Set reset vector based on the configured property valueBin Meng1-0/+2
2020-08-25hw/riscv: Allow creating multiple instances of PLICAnup Patel1-1/+1
2020-08-25hw/riscv: Allow creating multiple instances of CLINTAnup Patel1-1/+1
2020-08-21hw/riscv: Use pre-built bios image of generic platform for virt & sifive_uBin Meng1-2/+2
2020-08-21hw/riscv: sifive_u: Add a dummy L2 cache controller deviceBin Meng1-0/+22
2020-07-21hw: Mark nd_table[] misuse in realize methods FIXMEMarkus Armbruster1-0/+1
2020-07-13hw/riscv: Modify MROM size to end at 0x10000Bin Meng1-1/+1
2020-07-13RISC-V: Support 64 bit start addressAtish Patra1-1/+5
2020-07-13riscv: Add opensbi firmware dynamic supportAtish Patra1-5/+15
2020-07-13RISC-V: Copy the fdt in dram instead of ROMAtish Patra1-15/+13
2020-07-13riscv: Unify Qemu's reset vector code pathAtish Patra1-1/+0
2020-07-10error: Eliminate error_propagate() with Coccinelle, part 1Markus Armbruster1-3/+1
2020-07-10qom: Put name parameter before value / visitor parameterMarkus Armbruster1-3/+3
2020-07-10qdev: Use returned bool to check for qdev_realize() etc. failureMarkus Armbruster1-2/+1
2020-07-02riscv/sifive_u: Fix sifive_u_soc_realize() error API violationsMarkus Armbruster1-3/+9
2020-06-19hw/riscv: sifive_u: Add a dummy DDR memory controller deviceBin Meng1-0/+4
2020-06-19hw/riscv: sifive_u: Sort the SoC memmap table entriesBin Meng1-2/+2
2020-06-19hw/riscv: sifive_u: Support different boot source per MSEL pin stateBin Meng1-8/+31
2020-06-19hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004Bin Meng1-3/+3
2020-06-19hw/riscv: sifive_u: Add a new property msel for MSEL pin stateBin Meng1-0/+7
2020-06-19hw/riscv: sifive_u: Rename serial property get/set functions to a generic nameBin Meng1-6/+8
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