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riscv
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sifive_u.c
Age
Commit message (
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Author
Files
Lines
2021-09-21
hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines
Alistair Francis
1
-1
/
+1
2021-08-26
arch_init.h: Don't include arch_init.h unnecessarily
Peter Maydell
1
-1
/
+0
2021-07-15
hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned
Bin Meng
1
-2
/
+3
2021-07-15
hw/riscv: sifive_u: Correct the CLINT timebase frequency
Bin Meng
1
-2
/
+5
2021-06-08
hw/riscv: Use macros for BIOS image names
Bin Meng
1
-4
/
+2
2021-06-08
hw/riscv: Support the official PLIC DT bindings
Bin Meng
1
-1
/
+5
2021-06-08
hw/riscv: Support the official CLINT DT bindings
Bin Meng
1
-1
/
+5
2021-06-08
hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper
Bin Meng
1
-3
/
+3
2021-05-02
hw: Do not include qemu/log.h if it is not necessary
Thomas Huth
1
-1
/
+0
2021-03-04
hw/riscv: Drop 'struct MemmapEntry'
Bin Meng
1
-7
/
+4
2021-03-04
hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card
Bin Meng
1
-2
/
+41
2021-03-04
hw/riscv: sifive_u: Add QSPI0 controller and connect a flash
Bin Meng
1
-0
/
+52
2021-01-16
riscv: Pass RISCVHartArrayState by pointer
Alistair Francis
1
-5
/
+5
2021-01-16
hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type
Bin Meng
1
-5
/
+1
2020-12-17
hw/riscv: Use the CPU to determine if 32-bit
Alistair Francis
1
-5
/
+5
2020-12-17
hw/riscv: sifive_u: Remove compile time XLEN checks
Alistair Francis
1
-25
/
+30
2020-12-17
hw/riscv: boot: Remove compile time XLEN checks
Alistair Francis
1
-1
/
+1
2020-12-17
hw/riscv: sifive_u: Add UART1 DT node in the generated DTB
Anup Patel
1
-0
/
+15
2020-12-15
vl: make qemu_get_machine_opts static
Paolo Bonzini
1
-4
/
+2
2020-11-03
hw/riscv: sifive_u: Allow passing custom DTB
Anup Patel
1
-8
/
+20
2020-10-22
hw/riscv: Load the kernel after the firmware
Alistair Francis
1
-2
/
+8
2020-10-22
hw/riscv: sifive_u: Allow specifying the CPU
Alistair Francis
1
-5
/
+13
2020-09-22
sifive_u: Register "start-in-flash" as class property
Eduardo Habkost
1
-8
/
+8
2020-09-18
sifive_u: Rename memmap enum constants
Eduardo Habkost
1
-78
/
+78
2020-09-09
hw/riscv: Move sifive_uart model to hw/char
Bin Meng
1
-1
/
+1
2020-09-09
hw/riscv: Move sifive_plic model to hw/intc
Bin Meng
1
-1
/
+1
2020-09-09
hw/riscv: Move sifive_clint model to hw/intc
Bin Meng
1
-1
/
+1
2020-09-09
hw/riscv: sifive_u: Connect a DMA controller
Bin Meng
1
-0
/
+30
2020-09-09
hw/riscv: clint: Avoid using hard-coded timebase frequency
Bin Meng
1
-1
/
+2
2020-09-09
target/riscv: cpu: Set reset vector based on the configured property value
Bin Meng
1
-0
/
+2
2020-08-25
hw/riscv: Allow creating multiple instances of PLIC
Anup Patel
1
-1
/
+1
2020-08-25
hw/riscv: Allow creating multiple instances of CLINT
Anup Patel
1
-1
/
+1
2020-08-21
hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u
Bin Meng
1
-2
/
+2
2020-08-21
hw/riscv: sifive_u: Add a dummy L2 cache controller device
Bin Meng
1
-0
/
+22
2020-07-21
hw: Mark nd_table[] misuse in realize methods FIXME
Markus Armbruster
1
-0
/
+1
2020-07-13
hw/riscv: Modify MROM size to end at 0x10000
Bin Meng
1
-1
/
+1
2020-07-13
RISC-V: Support 64 bit start address
Atish Patra
1
-1
/
+5
2020-07-13
riscv: Add opensbi firmware dynamic support
Atish Patra
1
-5
/
+15
2020-07-13
RISC-V: Copy the fdt in dram instead of ROM
Atish Patra
1
-15
/
+13
2020-07-13
riscv: Unify Qemu's reset vector code path
Atish Patra
1
-1
/
+0
2020-07-10
error: Eliminate error_propagate() with Coccinelle, part 1
Markus Armbruster
1
-3
/
+1
2020-07-10
qom: Put name parameter before value / visitor parameter
Markus Armbruster
1
-3
/
+3
2020-07-10
qdev: Use returned bool to check for qdev_realize() etc. failure
Markus Armbruster
1
-2
/
+1
2020-07-02
riscv/sifive_u: Fix sifive_u_soc_realize() error API violations
Markus Armbruster
1
-3
/
+9
2020-06-19
hw/riscv: sifive_u: Add a dummy DDR memory controller device
Bin Meng
1
-0
/
+4
2020-06-19
hw/riscv: sifive_u: Sort the SoC memmap table entries
Bin Meng
1
-2
/
+2
2020-06-19
hw/riscv: sifive_u: Support different boot source per MSEL pin state
Bin Meng
1
-8
/
+31
2020-06-19
hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
Bin Meng
1
-3
/
+3
2020-06-19
hw/riscv: sifive_u: Add a new property msel for MSEL pin state
Bin Meng
1
-0
/
+7
2020-06-19
hw/riscv: sifive_u: Rename serial property get/set functions to a generic name
Bin Meng
1
-6
/
+8
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