Age | Commit message (Expand) | Author | Files | Lines |
2023-09-01 | hw/sd: Introduce a "sd-card" SPI variant model | Cédric Le Goater | 1 | -2/+1 |
2023-03-01 | hw/riscv: Move the dtb load bits outside of create_fdt() | Bin Meng | 1 | -16/+15 |
2023-03-01 | hw/riscv: Skip re-generating DT nodes for a given DTB | Bin Meng | 1 | -0/+1 |
2023-02-16 | hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() | Daniel Henrique Barboza | 1 | -10/+1 |
2023-02-16 | hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel() | Daniel Henrique Barboza | 1 | -1/+2 |
2023-02-07 | hw/riscv: change riscv_compute_fdt_addr() semantics | Daniel Henrique Barboza | 1 | -1/+2 |
2023-02-07 | hw/riscv: split fdt address calculation from fdt load | Daniel Henrique Barboza | 1 | -3/+4 |
2023-01-20 | hw/riscv/sifive_u.c: simplify create_fdt() | Daniel Henrique Barboza | 1 | -4/+4 |
2023-01-20 | hw/riscv/boot.c: use MachineState in riscv_load_kernel() | Daniel Henrique Barboza | 1 | -2/+1 |
2023-01-20 | hw/riscv/boot.c: use MachineState in riscv_load_initrd() | Daniel Henrique Barboza | 1 | -2/+1 |
2023-01-20 | hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel() | Daniel Henrique Barboza | 1 | -6/+5 |
2023-01-20 | hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd() | Daniel Henrique Barboza | 1 | -8/+2 |
2023-01-20 | hw/riscv/sifive_u: use 'fdt' from MachineState | Daniel Henrique Barboza | 1 | -9/+6 |
2023-01-20 | hw/riscv/boot.c: introduce riscv_default_firmware_name() | Daniel Henrique Barboza | 1 | -7/+4 |
2023-01-06 | hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev" | Bin Meng | 1 | -1/+2 |
2022-10-17 | hw/riscv: set machine->fdt in sifive_u_machine_init() | Daniel Henrique Barboza | 1 | -0/+3 |
2022-05-24 | hw/riscv/sifive_u: Resolve redundant property accessors | Bernhard Beschow | 1 | -20/+4 |
2022-05-24 | hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan) | Tsukasa OI | 1 | -2/+2 |
2022-04-29 | hw/riscv: Don't add empty bootargs to device tree | Bin Meng | 1 | -1/+1 |
2022-01-08 | hw/riscv: Use error_fatal for SoC realisation | Alistair Francis | 1 | -1/+1 |
2021-12-15 | hw: Replace trivial drive_get_next() by drive_get() | Markus Armbruster | 1 | -1/+1 |
2021-12-15 | hw/sd/ssi-sd: Do not create SD card within controller's realize | Markus Armbruster | 1 | -1/+12 |
2021-10-28 | hw/riscv: sifive_u: Use the PLIC config helper function | Alistair Francis | 1 | -13/+1 |
2021-10-22 | hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id | Bin Meng | 1 | -4/+2 |
2021-09-21 | hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT | Anup Patel | 1 | -3/+6 |
2021-09-21 | hw/intc: Rename sifive_clint sources to riscv_aclint sources | Anup Patel | 1 | -1/+1 |
2021-09-21 | sifive_u: Connect the SiFive PWM device | Alistair Francis | 1 | -1/+54 |
2021-09-21 | hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines | Alistair Francis | 1 | -1/+1 |
2021-08-26 | arch_init.h: Don't include arch_init.h unnecessarily | Peter Maydell | 1 | -1/+0 |
2021-07-15 | hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned | Bin Meng | 1 | -2/+3 |
2021-07-15 | hw/riscv: sifive_u: Correct the CLINT timebase frequency | Bin Meng | 1 | -2/+5 |
2021-06-08 | hw/riscv: Use macros for BIOS image names | Bin Meng | 1 | -4/+2 |
2021-06-08 | hw/riscv: Support the official PLIC DT bindings | Bin Meng | 1 | -1/+5 |
2021-06-08 | hw/riscv: Support the official CLINT DT bindings | Bin Meng | 1 | -1/+5 |
2021-06-08 | hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper | Bin Meng | 1 | -3/+3 |
2021-05-02 | hw: Do not include qemu/log.h if it is not necessary | Thomas Huth | 1 | -1/+0 |
2021-03-04 | hw/riscv: Drop 'struct MemmapEntry' | Bin Meng | 1 | -7/+4 |
2021-03-04 | hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card | Bin Meng | 1 | -2/+41 |
2021-03-04 | hw/riscv: sifive_u: Add QSPI0 controller and connect a flash | Bin Meng | 1 | -0/+52 |
2021-01-16 | riscv: Pass RISCVHartArrayState by pointer | Alistair Francis | 1 | -5/+5 |
2021-01-16 | hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type | Bin Meng | 1 | -5/+1 |
2020-12-17 | hw/riscv: Use the CPU to determine if 32-bit | Alistair Francis | 1 | -5/+5 |
2020-12-17 | hw/riscv: sifive_u: Remove compile time XLEN checks | Alistair Francis | 1 | -25/+30 |
2020-12-17 | hw/riscv: boot: Remove compile time XLEN checks | Alistair Francis | 1 | -1/+1 |
2020-12-17 | hw/riscv: sifive_u: Add UART1 DT node in the generated DTB | Anup Patel | 1 | -0/+15 |
2020-12-15 | vl: make qemu_get_machine_opts static | Paolo Bonzini | 1 | -4/+2 |
2020-11-03 | hw/riscv: sifive_u: Allow passing custom DTB | Anup Patel | 1 | -8/+20 |
2020-10-22 | hw/riscv: Load the kernel after the firmware | Alistair Francis | 1 | -2/+8 |
2020-10-22 | hw/riscv: sifive_u: Allow specifying the CPU | Alistair Francis | 1 | -5/+13 |
2020-09-22 | sifive_u: Register "start-in-flash" as class property | Eduardo Habkost | 1 | -8/+8 |