riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-07-10	qdev: Use returned bool to check for qdev_realize() etc. failure	Markus Armbruster	1	-2/+1
2020-07-02	riscv/sifive_u: Fix sifive_u_soc_realize() error API violations	Markus Armbruster	1	-3/+9
2020-06-19	hw/riscv: sifive_u: Add a dummy DDR memory controller device	Bin Meng	1	-0/+4
2020-06-19	hw/riscv: sifive_u: Sort the SoC memmap table entries	Bin Meng	1	-2/+2
2020-06-19	hw/riscv: sifive_u: Support different boot source per MSEL pin state	Bin Meng	1	-8/+31
2020-06-19	hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004	Bin Meng	1	-3/+3
2020-06-19	hw/riscv: sifive_u: Add a new property msel for MSEL pin state	Bin Meng	1	-0/+7
2020-06-19	hw/riscv: sifive_u: Rename serial property get/set functions to a generic name	Bin Meng	1	-6/+8
2020-06-19	hw/riscv: sifive_u: Add reset functionality	Bin Meng	1	-1/+23
2020-06-19	hw/riscv: sifive_u: Hook a GPIO controller	Bin Meng	1	-2/+41
2020-06-19	hw/riscv: sifive_u: Generate device tree node for OTP	Bin Meng	1	-0/+11
2020-06-19	hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit	Bin Meng	1	-6/+1
2020-06-15	qdev: Convert bus-less devices to qdev_realize() with Coccinelle	Markus Armbruster	1	-6/+3
2020-06-15	sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2	Markus Armbruster	1	-19/+12
2020-06-15	qom: Less verbose object_initialize_child()	Markus Armbruster	1	-9/+3
2020-06-15	riscv: Fix to put "riscv.hart_array" devices on sysbus	Markus Armbruster	1	-8/+6
2020-06-03	hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions	Bin Meng	1	-12/+12
2020-05-15	qom: Drop parameter @errp of object_property_add() & friends	Markus Armbruster	1	-4/+6
2020-05-15	qom: Drop object_property_set_description() parameter @errp	Markus Armbruster	1	-3/+2
2020-04-29	hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()	Anup Patel	1	-1/+1
2020-04-29	hw/riscv: Generate correct "mmu-type" for 32-bit machines	Bin Meng	1	-0/+4
2020-04-29	riscv/sifive_u: Add a serial property to the sifive_u machine	Bin Meng	1	-0/+20
2020-04-29	riscv/sifive_u: Add a serial property to the sifive_u SoC	Alistair Francis	1	-1/+7
2020-04-29	riscv/sifive_u: Fix up file ordering	Alistair Francis	1	-54/+54
2020-04-29	various: Remove suspicious '\' character outside of #define in C code	Philippe Mathieu-Daudé	1	-1/+1
2020-03-17	Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging	Peter Maydell	1	-1/+1
2020-03-17	hw/riscv: Let devices own the MemoryRegion they create	Philippe Mathieu-Daudé	1	-1/+1
2020-03-16	riscv: sifive_u: Update BIOS_FILENAME for 32-bit	Bin Meng	1	-1/+5
2020-02-27	hw/riscv: Provide rdtime callback for TCG in CLINT emulation	Anup Patel	1	-1/+1
2020-01-16	riscv/sifive_u: fix a memory leak in soc_realize()	Pan Nengyuan	1	-0/+1
2019-11-25	hw/riscv: Add optional symbol callback ptr to riscv_load_kernel()	Zhuang, Siwei (Data61, Kensington NSW)	1	-1/+2
2019-10-28	riscv/sifive_u: Add the start-in-flash property	Alistair Francis	1	-1/+29
2019-10-28	riscv/sifive_u: Manually define the machine	Alistair Francis	1	-13/+31
2019-10-28	riscv/sifive_u: Add QSPI memory region	Alistair Francis	1	-0/+8
2019-10-28	riscv/sifive_u: Add L2-LIM cache memory	Alistair Francis	1	-0/+16
2019-10-28	riscv: sifive_u: Add ethernet0 to the aliases node	Bin Meng	1	-1/+4
2019-10-28	riscv: hw: Drop "clock-frequency" property of cpu nodes	Bin Meng	1	-2/+0
2019-09-17	riscv: sifive_u: Update model and compatible strings in device tree	Bin Meng	1	-2/+3
2019-09-17	riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet	Bin Meng	1	-23/+1
2019-09-17	riscv: sifive_u: Fix broken GEM support	Bin Meng	1	-4/+20
2019-09-17	riscv: sifive_u: Instantiate OTP memory with a serial number	Bin Meng	1	-0/+9
2019-09-17	riscv: sifive_u: Change UART node name in device tree	Bin Meng	1	-1/+1
2019-09-17	riscv: sifive_u: Update UART base addresses and IRQs	Bin Meng	1	-2/+2
2019-09-17	riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes	Bin Meng	1	-3/+4
2019-09-17	riscv: sifive_u: Add PRCI block to the SoC	Bin Meng	1	-1/+23
2019-09-17	riscv: sifive_u: Generate hfclk and rtcclk nodes	Bin Meng	1	-0/+23
2019-09-17	riscv: sifive_u: Update PLIC hart topology configuration string	Bin Meng	1	-3/+4
2019-09-17	riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC	Bin Meng	1	-25/+67
2019-09-17	riscv: sifive_u: Set the minimum number of cpus to 2	Bin Meng	1	-1/+4
2019-09-17	riscv: sifive_u: Remove the unnecessary include of prci header	Bin Meng	1	-1/+0