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AgeCommit message (Expand)AuthorFilesLines
2019-12-17ppc/pnv: Drop PnvChipClass::typeGreg Kurz1-5/+0
2019-12-17ppc/pnv: Introduce PnvChipClass::xscom_pcba() methodGreg Kurz2-13/+24
2019-12-17ppc/pnv: Pass content of the "compatible" property to pnv_dt_xscom()Greg Kurz2-20/+12
2019-12-17ppc/pnv: Pass XSCOM base address and address size to pnv_dt_xscom()Greg Kurz2-16/+12
2019-12-17ppc/pnv: Introduce PnvChipClass::xscom_core_base() methodGreg Kurz1-7/+24
2019-12-17ppc/pnv: Introduce PnvChipClass::intc_print_info() methodGreg Kurz1-5/+25
2019-12-17ppc/pnv: Introduce PnvMachineClass::dt_power_mgt()Greg Kurz1-4/+6
2019-12-17ppc/pnv: Introduce PnvMachineClass and PnvMachineClass::compatGreg Kurz1-14/+18
2019-12-17ppc/pnv: Drop PnvPsiClass::chip_typeGreg Kurz1-3/+0
2019-12-17ppc/pnv: Introduce PnvPsiClass::compatGreg Kurz1-14/+11
2019-12-17ppc/pnv: Fix OCC common area region mappingCédric Le Goater2-9/+6
2019-12-17ppc/pnv: Introduce PBA registersCédric Le Goater3-34/+119
2019-12-17ppc/pnv: populate the DT with realized XSCOM devicesCédric Le Goater1-1/+4
2019-12-17ppc/pnv: Loop on the whole hierarchy to populate the DT with the XSCOM nodesCédric Le Goater1-1/+6
2019-12-17target/ppc: Add SPR TBU40Suraj Jitindar Singh1-0/+13
2019-12-17target/ppc: Work [S]PURR implementation and add HV supportSuraj Jitindar Singh1-10/+7
2019-12-17target/ppc: Implement the VTB for HV accessSuraj Jitindar Singh1-0/+16
2019-12-17ppc/pnv: add a LPC Controller model for POWER10Cédric Le Goater2-11/+44
2019-12-17ppc/pnv: add a PSI bridge model for POWER10Cédric Le Goater2-8/+44
2019-12-17ppc/psi: cleanup definitionsCédric Le Goater1-2/+5
2019-12-17ppc/pnv: Introduce a POWER10 PnvChip and a powernv10 machineCédric Le Goater3-11/+180
2019-12-17ppc: Don't use CPUPPCState::irq_input_state with modern Book3s CPU modelsGreg Kurz1-14/+2
2019-12-17ppc: Deassert the external interrupt pin in KVM on resetGreg Kurz1-0/+8
2019-12-17spapr: Simplify ovec diffDavid Gibson3-37/+15
2019-12-17spapr: Fold h_cas_compose_response() into h_client_architecture_support()David Gibson2-63/+53
2019-12-17spapr: Improve handling of fdt buffer sizeDavid Gibson1-22/+11
2019-12-17spapr: Don't trigger a CAS reboot for XICS/XIVE mode changeoverDavid Gibson1-20/+13
2019-12-17ppc: well form kvmppc_hint_smt_possible error hint helperVladimir Sementsov-Ogievskiy1-1/+1
2019-12-17ppc/pnv: Clarify how the TIMA is accessed on a multichip systemCédric Le Goater1-0/+14
2019-12-17spapr: Pass the maximum number of vCPUs to the KVM interrupt controllerGreg Kurz1-3/+5
2019-12-17ppc/spapr: Implement the XiveFabric interfaceCédric Le Goater1-0/+39
2019-12-17ppc/pnv: Implement the XiveFabric interfaceCédric Le Goater1-0/+35
2019-12-17ppc/pnv: Fix TIMA indirect accessCédric Le Goater1-0/+17
2019-12-17ppc: Introduce a ppc_cpu_pir() helperCédric Le Goater1-2/+7
2019-12-17ppc/pnv: Instantiate cores separatelyGreg Kurz1-18/+12
2019-12-17ppc/pnv: Create BMC devices at machine initCédric Le Goater2-20/+33
2019-12-17ppc/pnv: Add HIOMAP commandsCédric Le Goater3-0/+116
2019-12-17ppc/pnv: Add a LPC "ranges" propertyCédric Le Goater1-1/+13
2019-12-17spapr: Abort if XICS interrupt controller cannot be initializedGreg Kurz1-11/+2
2019-12-17xics: Link ICS_PROP_XICS property to ICSState::xics pointerGreg Kurz2-9/+3
2019-12-17ppc/pnv: Link "chip" property to PnvXive::chip pointerGreg Kurz1-2/+2
2019-12-17ppc/pnv: Link "chip" property to PnvCore::chip pointerGreg Kurz2-10/+4
2019-12-17ppc/pnv: Link "chip" property to PnvHomer::chip pointerGreg Kurz2-14/+14
2019-12-17ppc/pnv: Link "psi" property to PnvOCC::psi pointerGreg Kurz2-15/+13
2019-12-17ppc/pnv: Link "psi" property to PnvLpc::psi pointerGreg Kurz2-15/+12
2019-12-17xive: Link "xive" property to XiveSource::xive pointerGreg Kurz1-2/+1
2019-12-17ppc/pnv: Drop "chip" link from POWER9 PSI objectGreg Kurz1-2/+0
2019-12-17ppc/pnv: Add a "/qemu" device tree nodeCédric Le Goater1-0/+3
2019-12-17ppc/pnv: Add a PNOR modelCédric Le Goater3-1/+152
2019-12-14hw: add compat machines for 5.0Cornelia Huck1-1/+12
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