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path: root/hw/ppc/spapr_hcall.c
AgeCommit message (Expand)AuthorFilesLines
2017-01-31ppc: Add ppc_set_compat_all()David Gibson1-26/+5
2017-01-31pseries: Rewrite CAS PVR compatibility logicDavid Gibson1-71/+33
2017-01-31ppc/spapr: implement H_SIGNAL_SYS_RESETNicholas Piggin1-0/+41
2017-01-31ppc: Rename cpu_version to compat_pvrDavid Gibson1-15/+15
2017-01-31pseries: Make cpu_update during CAS unconditionalDavid Gibson1-6/+2
2017-01-19kvm: move cpu synchronization codeVincent Palatin1-1/+1
2016-10-31Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream-mttcg' into s...Peter Maydell1-6/+6
2016-10-31*_run_on_cpu: introduce run_on_cpu_data typePaolo Bonzini1-6/+6
2016-10-28spapr: add option vector handling in CAS-generated resetsMichael Roth1-4/+18
2016-10-28spapr_hcall: use spapr_ovec_* interfaces for CAS optionsMichael Roth1-41/+15
2016-09-27cpus: pass CPUState to run_on_cpu helpersAlex Bennée1-10/+7
2016-09-23target-ppc: tlbie/tlbivax should have global effectNikunj A Dadhania1-0/+2
2016-09-23target-ppc: add flag in check_tlb_flush()Nikunj A Dadhania1-2/+2
2016-07-05ppc: simplify ppc_hash64_hpte_page_shift_noslb()Cédric Le Goater1-2/+2
2016-06-22powerpc/mm: Update the WIMG check during H_ENTERAneesh Kumar K.V1-1/+5
2016-06-14ppc: Add PowerISA 2.07 compatibility modeThomas Huth1-2/+4
2016-06-14ppc: Split pcr_mask settings into supported bits and the register maskThomas Huth1-2/+2
2016-06-14ppc/spapr: Refactor h_client_architecture_support() CPU parsing codeThomas Huth1-25/+36
2016-05-30ppc: Do some batching of TCG tlb flushesBenjamin Herrenschmidt1-3/+11
2016-05-19cpu: move exec-all.h inclusion out of cpu.hPaolo Bonzini1-0/+1
2016-05-19hw: explicitly include qemu/log.hPaolo Bonzini1-0/+1
2016-05-19dma: do not depend on kvm_enabled()Paolo Bonzini1-0/+1
2016-04-05ppc: Rework POWER7 & POWER8 exception modelCédric Le Goater1-15/+1
2016-03-22include/qemu/osdep.h: Don't include qapi/error.hMarkus Armbruster1-0/+1
2016-03-16target-ppc: Eliminate kvmppc_kern_htab globalDavid Gibson1-5/+5
2016-02-25hw/ppc/spapr: Implement the h_page_init hypercallThomas Huth1-0/+60
2016-02-17hw/ppc/spapr: Implement the h_set_xdabr hypercallThomas Huth1-0/+22
2016-02-17hw/ppc/spapr: Implement h_set_dabrThomas Huth1-5/+20
2016-02-17hw/ppc/spapr: Add h_set_sprg0 hypercallThomas Huth1-2/+13
2016-01-30target-ppc: Helper to determine page size information from hpte aloneDavid Gibson1-19/+6
2016-01-30target-ppc: Add new TLB invalidate by HPTE call for hash64 MMUsDavid Gibson1-42/+4
2016-01-30target-ppc: Convert mmu-hash{32,64}.[ch] from CPUPPCState to PowerPCCPUDavid Gibson1-16/+15
2016-01-30pseries: Allow TCG h_enter to work with hotplugged memoryDavid Gibson1-2/+17
2016-01-30ppc: Clean up error handling in ppc_set_compat()David Gibson1-5/+5
2016-01-30spapr: Remove abuse of rtas_ld() in h_client_architecture_supportDavid Gibson1-7/+7
2016-01-29ppc: Clean up includesPeter Maydell1-0/+1
2015-09-23spapr: Support ibm,dynamic-reconfiguration-memoryBharata B Rao1-6/+45
2015-09-23ppc/spapr: Use qemu_log_mask() for hcall_dprintf()Thomas Huth1-1/+2
2015-07-07spapr: Remove obsolete ram_limit field from sPAPRMachineStateDavid Gibson1-1/+2
2015-07-07spapr: Merge sPAPREnvironment into sPAPRMachineStateDavid Gibson1-17/+19
2015-03-09pseries: Switch VGA endian on H_SET_MODEDavid Gibson1-0/+2
2014-09-08hw/ppc/spapr_hcall.c: Fix typo in function namesPeter Maydell1-11/+11
2014-07-08hw/ppc/spapr_hcall.c: Add ULL suffix to 64 bit constantPeter Maydell1-1/+1
2014-06-16spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODEAlexey Kardashevskiy1-0/+47
2014-06-16spapr_hcall: Split h_set_mode()Alexey Kardashevskiy1-31/+34
2014-06-16spapr: Implement processor compatibility in ibm, client-architecture-supportAlexey Kardashevskiy1-0/+106
2014-06-16spapr: Add ibm, client-architecture-support callAlexey Kardashevskiy1-0/+21
2014-03-20spapr_hcall: Fix little-endian resource handling in H_SET_MODEAlexey Kardashevskiy1-8/+33
2014-03-20spapr_hcall: Fix h_enter to loop correctlyAneesh Kumar K.V1-6/+5
2014-03-13cpu: Move exception_index field from CPU_COMMON to CPUStateAndreas Färber1-1/+1
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