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path: root/hw/pci-bridge
AgeCommit message (Expand)AuthorFilesLines
2023-03-07hw/pxb-cxl: Support passthrough HDM Decoders unless overriddenJonathan Cameron1-5/+39
2023-03-07hw/pci-bridge/cxl_root_port: Wire up MSIJonathan Cameron1-0/+61
2023-03-07hw/pci-bridge/cxl_root_port: Wire up AERJonathan Cameron1-0/+3
2023-03-02hw/pci-bridge/cxl_downstream: Fix type naming mismatchJonathan Cameron1-1/+1
2023-02-27hw: Move ich9.h to southbridge/Bernhard Beschow1-1/+1
2023-01-28pci: acpi hotplug: rename x-native-hotplug to x-do-not-expose-native-hotplug-capIgor Mammedov1-1/+6
2023-01-28pci_bridge: remove whitespaceIgor Mammedov1-1/+0
2023-01-18bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plxPhilippe Mathieu-Daudé1-1/+1
2023-01-08include/hw/cxl: Move typedef PXBDev to cxl.h, and put it to useMarkus Armbruster1-1/+0
2023-01-08include/hw/pci: Break inclusion loop pci_bridge.h and cxl.hMarkus Armbruster1-1/+1
2022-12-21pci: drop redundant PCIDeviceClass::is_bridge fieldIgor Mammedov9-9/+0
2022-12-21remove DEC 21154 PCI bridgeIgor Mammedov3-175/+0
2022-12-16pci: Convert child classes of TYPE_PCIE_ROOT_PORT to 3-phase resetPeter Maydell1-5/+9
2022-12-16pci: Convert TYPE_PCIE_ROOT_PORT to 3-phase resetPeter Maydell1-3/+5
2022-11-07hw/pci-bridge/cxl-upstream: Add a CDAT table access DOEJonathan Cameron1-1/+194
2022-06-16pci-bridge/cxl_downstream: Add a CXL switch downstream portJonathan Cameron2-1/+250
2022-06-16pci-bridge/cxl_upstream: Add a CXL switch upstream portJonathan Cameron2-1/+217
2022-06-09pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.Jonathan Cameron3-13/+38
2022-06-09hw/cxl: Make the CXL fixed memory window setup a machine parameter.Jonathan Cameron1-1/+1
2022-05-13CXL/cxl_component: Add cxl_get_hb_cstate()Jonathan Cameron1-0/+7
2022-05-13acpi/cxl: Create the CEDT (9.14.1)Ben Widawsky1-17/+0
2022-05-13hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142)Ben Widawsky1-7/+59
2022-05-13hw/cxl/rp: Add a root portBen Widawsky4-1/+247
2022-05-13hw/pxb: Allow creation of a CXL PXB (host bridge)Ben Widawsky1-2/+84
2022-05-13hw/pci/cxl: Create a CXL bus typeBen Widawsky1-1/+8
2022-05-13hw/pxb: Use a type for realizing expandersBen Widawsky1-4/+7
2022-03-06pci: expose TYPE_XIO3130_DOWNSTREAM nameIgor Mammedov1-1/+2
2022-03-06pci-bridge/xio3130_downstream: Fix error handlingJonathan Cameron1-1/+1
2022-03-06pci-bridge/xio3130_upstream: Fix error handlingJonathan Cameron1-1/+1
2022-03-06hw/pci-bridge/pxb: Fix missing swizzleJonathan Cameron1-0/+6
2021-10-15qdev: Make DeviceState.id independent of QemuOptsKevin Wolf1-1/+1
2021-08-03hw/pcie-root-port: Fix hotplug for PCI devices requiring IOMarcel Apfelbaum1-0/+5
2021-07-16hw/pxb: Add a bypass iommu propertyXingang Wang1-0/+3
2021-01-17Kconfig: Compile PXB for ARM_VIRTJiahui Cen1-1/+1
2020-12-18qdev: Move softmmu properties to qdev-properties-system.hEduardo Habkost1-0/+1
2020-11-15nomaintainer: Fix Lesser GPL version numberChetan Pant1-1/+1
2020-09-18Use OBJECT_DECLARE_SIMPLE_TYPE when possibleEduardo Habkost4-12/+4
2020-09-09Use DECLARE_*CHECKER* macrosEduardo Habkost5-11/+16
2020-09-09Move QOM typedefs and add missing includesEduardo Habkost5-11/+21
2020-08-21meson: convert hw/pci-bridgeMarc-André Lureau2-10/+14
2020-06-15sysbus: Convert to sysbus_realize() etc. with CoccinelleMarkus Armbruster1-1/+1
2020-06-15pci: Convert uses of pci_create() etc. with CoccinelleMarkus Armbruster1-3/+3
2020-06-15qdev: Convert uses of qdev_create() manuallyMarkus Armbruster1-2/+2
2020-06-15qdev: Convert uses of qdev_create() with CoccinelleMarkus Armbruster1-2/+2
2020-05-27hw/pci-bridge/dec: Remove dead debug codePhilippe Mathieu-Daudé1-10/+0
2020-03-08pcie_root_port: Add hotplug disabling optionJulia Suvorova2-2/+2
2020-01-24qdev: set properties with device_class_set_props()Marc-André Lureau6-7/+7
2019-09-03numa: move numa global variable nb_numa_nodes into MachineStateTao Xu1-1/+8
2019-08-16Include hw/qdev-properties.h lessMarkus Armbruster6-0/+6
2019-08-16Include migration/vmstate.h lessMarkus Armbruster5-0/+5
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