| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2024-04-25 | hw, target: Add ResetType argument to hold and exit phase methods | Peter Maydell | 1 | -2/+2 |
| 2024-03-12 | bulk: Access existing variables initialized to &S->F when available | Philippe Mathieu-Daudé | 1 | -1/+1 |
| 2024-02-14 | hw/cxl: Standardize all references on CXL r3.1 and minor updates | Jonathan Cameron | 1 | -2/+2 |
| 2023-11-07 | hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExt | Jonathan Cameron | 1 | -1/+1 |
| 2023-03-07 | hw/pci-bridge/cxl_root_port: Wire up MSI | Jonathan Cameron | 1 | -0/+61 |
| 2023-03-07 | hw/pci-bridge/cxl_root_port: Wire up AER | Jonathan Cameron | 1 | -0/+3 |
| 2022-12-16 | pci: Convert child classes of TYPE_PCIE_ROOT_PORT to 3-phase reset | Peter Maydell | 1 | -5/+9 |
| 2022-05-13 | hw/cxl/rp: Add a root port | Ben Widawsky | 1 | -0/+236 |
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index : riscv-gnu-toolchain/qemu.git | |
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