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path: root/hw/pci-bridge/cxl_downstream.c
AgeCommit message (Expand)AuthorFilesLines
2024-02-14hw/cxl: Standardize all references on CXL r3.1 and minor updatesJonathan Cameron1-2/+2
2023-11-07hw/pci-bridge/cxl_downstream: Set default link width and link speedJonathan Cameron1-0/+14
2023-11-07hw/cxl/mbox: Add Physical Switch Identify command.Jonathan Cameron1-3/+1
2023-11-07hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExtJonathan Cameron1-1/+1
2023-09-20hw/pci: spelling fixesMichael Tokarev1-1/+1
2023-03-02hw/pci-bridge/cxl_downstream: Fix type naming mismatchJonathan Cameron1-1/+1
2022-12-21pci: drop redundant PCIDeviceClass::is_bridge fieldIgor Mammedov1-1/+0
2022-06-16pci-bridge/cxl_downstream: Add a CXL switch downstream portJonathan Cameron1-0/+249