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2023-01-06Merge tag 'pull-riscv-to-apply-20230106' of https://github.com/alistair23/qem...Peter Maydell2-6/+90
2023-01-06hw/{misc, riscv}: pfsoc: add system controller as unimplementedConor Dooley2-6/+84
2023-01-06hw/misc: pfsoc: add fabric clocks to ioscbConor Dooley1-0/+6
2023-01-05i.MX6UL: Add a specific GPT timer instance for the i.MX6ULJean-Christophe Dubois1-6/+0
2023-01-05i.MX7D: Compute clock frequency for the fixed frequency clocks.Jean-Christophe Dubois1-9/+40
2022-12-16hw/misc: Convert TYPE_MOS6522 subclasses to 3-phase resetPeter Maydell3-22/+32
2022-12-16hw/misc/mos6522: Convert TYPE_MOS6522 to 3-phase resetPeter Maydell1-3/+4
2022-12-15hw/misc: Move some arm-related files from specific_ss into softmmu_ssThomas Huth3-8/+6
2022-10-31mac_nvram: Use NVRAM_SIZE constantBALATON Zoltan1-1/+1
2022-10-31hw/ppc/mac.h: Rename to include/hw/nvram/mac_nvram.hBALATON Zoltan4-4/+0
2022-10-31hw/ppc/mac.h: Move macio specific parts out from shared headerBALATON Zoltan1-2/+3
2022-10-22Drop useless casts from g_malloc() & friends to pointerMarkus Armbruster1-3/+3
2022-10-06monitor: expose monitor_puts to rest of codeAlex Bennée1-1/+1
2022-09-14hw/arm/bcm2835_property: Add support for RPI_FIRMWARE_FRAMEBUFFER_GET_NUM_DIS...Enrik Berkhan1-0/+4
2022-08-08hw/misc/grlib_ahb_apb_pnp: Support 8 and 16 bit accessesPeter Maydell2-6/+8
2022-08-01trivial: Fix duplicated wordsThomas Huth1-1/+1
2022-08-01misc: fix commonly doubled up wordsDaniel P. Berrangé2-3/+3
2022-07-14aspeed: sbc: Allow per-machine settingsJoel Stanley1-2/+40
2022-07-12block: Change blk_{pread,pwrite}() param orderAlberto Faria2-9/+9
2022-07-12block: Add a 'flags' param to blk_pread()Alberto Faria2-3/+3
2022-07-12block: Make blk_{pread,pwrite}() return 0 on successAlberto Faria2-3/+3
2022-06-30hw/misc/aspeed: Add PECI controllerPeter Delevoryas3-1/+159
2022-06-30aspeed/hace: Accumulative mode supportedJoel Stanley1-3/+3
2022-06-30aspeed/scu: Add trace events for read opsCédric Le Goater2-0/+3
2022-06-22aspeed/hace: Add missing newlines to unimp messagesJoel Stanley1-2/+2
2022-06-09acpi: pvpanic-isa: use AcpiDevAmlIfClass:build_dev_aml to provide device's AMLIgor Mammedov1-0/+42
2022-06-09acpi: applesmc: use AcpiDevAmlIfClass:build_dev_aml to provide device's AMLIgor Mammedov1-0/+29
2022-05-08lasi: move from hw/hppa to hw/miscMark Cave-Ayland4-0/+285
2022-05-03Merge tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qemu into stagingRichard Henderson1-1/+1
2022-05-03Use g_unix_set_fd_nonblocking()Marc-André Lureau1-1/+1
2022-05-03aspeed/hace: Support AST1030 HACESteven Lee1-0/+20
2022-05-02aspeed/hace: Support AST2600 HACESteven Lee1-5/+127
2022-05-02aspeed/hace: Support HMAC Key Buffer register.Steven Lee1-0/+7
2022-05-02aspeed/scu: Add AST1030 supportSteven Lee1-0/+63
2022-05-02aspeed: sbc: Correct default reset valuesJoel Stanley1-2/+5
2022-05-02hw: aspeed_scu: Introduce clkin_25Mhz attributeSteven Lee1-1/+5
2022-05-02hw: aspeed_scu: Add AST2600 apb_freq and hpll calculation functionSteven Lee1-1/+38
2022-04-21Merge tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qemu into stagingRichard Henderson1-1/+2
2022-04-21compiler.h: replace QEMU_NORETURN with G_NORETURNMarc-André Lureau1-1/+2
2022-04-21hw/misc: Add a model of the Xilinx Versal CRLEdgar E. Iglesias2-0/+422
2022-04-06Remove qemu-common.h include from most unitsMarc-André Lureau1-1/+0
2022-03-24hw: Fix misleading hexadecimal formatPhilippe Mathieu-Daudé1-2/+2
2022-03-21Use g_new() & friends where that makes obvious senseMarkus Armbruster3-4/+4
2022-03-18hw/misc: Add a model of the Xilinx ZynqMP APU ControlEdgar E. Iglesias2-0/+254
2022-03-18hw/misc: Add a model of the Xilinx ZynqMP CRFEdgar E. Iglesias2-0/+267
2022-03-18hw/misc/npcm7xx_clk: Don't leak string in npcm7xx_clk_sel_init()Peter Maydell1-2/+2
2022-03-15kvm/msi: do explicit commit when adding msi routesLongpeng(Mike)1-1/+4
2022-03-09macio/pmu.c: remove redundant codeMark Cave-Ayland1-33/+0
2022-03-09mos6522: implement edge-triggering for CA1/2 and CB1/2 control line IRQsMark Cave-Ayland2-8/+89
2022-03-09mac_via: make SCSI_DATA (DRQ) bit live rather than latchedMark Cave-Ayland1-1/+16
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