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2025-01-15hw/intc/loongarch_ipi: Use alternative implemation for cpu_by_arch_idBibo Mao1-25/+11
2025-01-15hw/intc/loongson_ipi: Add more input parameter for cpu_by_arch_idBibo Mao3-14/+49
2025-01-15hw/intc/loongarch_ipi: Remove property num-cpuBibo Mao1-5/+0
2025-01-15hw/intc/loongarch_ipi: Get cpu number from possible_cpu_arch_idsBibo Mao1-5/+8
2025-01-15hw/intc/loongson_ipi: Remove property num_cpu from loongson_ipi_commonBibo Mao3-6/+12
2025-01-15hw/intc/loongson_ipi: Remove num_cpu from loongson_ipi_commonBibo Mao3-15/+26
2025-01-15hw/intc/loongarch_ipi: Implement realize interfaceBibo Mao1-0/+19
2025-01-13hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bitPhilippe Mathieu-Daudé1-0/+4
2025-01-09hw/intc/loongarch_extioi: Add irq routing support from physical idBibo Mao1-4/+26
2025-01-09hw/intc/loongarch_extioi: Remove num-cpu propertyBibo Mao1-1/+0
2025-01-09hw/intc/loongarch_extioi: Get cpu number from possible_cpu_arch_idsBibo Mao2-8/+15
2025-01-07hw/s390x: Remove the "adapter_routes_max_batch" property from the flicThomas Huth1-9/+0
2024-12-21Merge tag 'exec-20241220' of https://github.com/philmd/qemu into stagingStefan Hajnoczi27-49/+49
2024-12-21Merge tag 'pull-riscv-to-apply-20241220' of https://github.com/alistair23/qem...Stefan Hajnoczi1-14/+60
2024-12-21Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi38-45/+0
2024-12-20include: Rename sysemu/ -> system/Philippe Mathieu-Daudé27-48/+48
2024-12-20hw/intc/riscv_aplic: add kvm_msicfgaddr for split mode aplic-imsicDaniel Henrique Barboza1-9/+33
2024-12-20hw/riscv/virt.c, riscv_aplic.c: add 'emulated_aplic' helpersDaniel Henrique Barboza1-3/+21
2024-12-20hw/intc/riscv_aplic: rename is_kvm_aia()Daniel Henrique Barboza1-4/+4
2024-12-20hw/intc/riscv_aplic: Fix APLIC in_clrip and clripnum write emulationYong-Xuan Wang1-1/+5
2024-12-19Merge tag 'pull-loongarch-20241219' of https://gitlab.com/bibo-mao/qemu into ...Stefan Hajnoczi5-148/+284
2024-12-19include/hw/qdev-properties: Remove DEFINE_PROP_END_OF_LISTRichard Henderson38-45/+0
2024-12-19hw/intc/loongarch_extioi: Code cleanup about loongarch_extioiBibo Mao1-17/+14
2024-12-19hw/intc/loongarch_extioi: Add pre_save interfaceBibo Mao1-0/+13
2024-12-19hw/intc/loongarch_extioi: Inherit from loongarch_extioi_commonBibo Mao3-22/+58
2024-12-19hw/intc/loongarch_extioi: Add common file loongarch_extioi_commonBibo Mao2-57/+65
2024-12-19hw/intc/loongarch_extioi: Add unrealize interfaceBibo Mao1-3/+3
2024-12-19hw/intc/loongarch_extioi: Add common realize interfaceBibo Mao1-2/+14
2024-12-19hw/intc/loongarch_extioi: Rename LoongArchExtIOI with LoongArchExtIOICommonStateBibo Mao1-16/+25
2024-12-19hw/intc/loongarch_pch: Code cleanup about loongarch_pch_picBibo Mao1-14/+10
2024-12-19hw/intc/loongarch_pch: Add pre_save and post_load interfacesBibo Mao1-0/+26
2024-12-19hw/intc/loongarch_pch: Inherit from loongarch_pic_commonBibo Mao3-22/+50
2024-12-19hw/intc/loongarch_pch: Move some functions to file loongarch_pic_commonBibo Mao2-36/+42
2024-12-19hw/intc/loongarch_pch: Rename LoongArchPCHPIC with LoongArchPICCommonStateBibo Mao1-20/+32
2024-12-19hw/intc/loongarch_pch: Merge instance_init() into realize()Bibo Mao1-11/+4
2024-12-17hw/intc/arm_gicv3_its: Zero initialize local DTEntry etc structsPeter Maydell1-22/+22
2024-12-15hw/intc: Constify all PropertyRichard Henderson38-45/+45
2024-11-19hw/intc/loongarch_extioi: Use set_bit32() and clear_bit32() for s->isrPeter Maydell1-8/+3
2024-11-19hw/intc/openpic: Avoid taking address of out-of-bounds array indexPeter Maydell1-7/+8
2024-11-04pnv/xive2: TIMA CI ops using alternative offsets or byte lengthsMichael Kowal1-0/+6
2024-11-04pnv/xive2: TIMA support for 8-byte OS context push for PHYPGlenn Miles2-5/+21
2024-11-04pnv/xive: Update PIPR when updating CPPRGlenn Miles1-2/+32
2024-11-04pnv/xive: Add special handling for pool targetsGlenn Miles1-10/+26
2024-11-04ppc/xive2: Support "Pull Thread Context to Odd Thread Reporting Line"Glenn Miles2-25/+57
2024-11-04ppc/xive2: Change context/ring specific functions to be genericMichael Kowal2-13/+13
2024-11-04ppc/xive2: Support "Pull Thread Context to Register" operationGlenn Miles1-0/+15
2024-11-04ppc/xive2: Allow 1-byte write of Target field in TIMAGlenn Miles2-0/+15
2024-11-04ppc/xive2: Dump the VP-group and crowd tables with 'info pic'Frederic Barrat2-3/+96
2024-11-04ppc/xive2: Dump more NVP state with 'info pic'Frederic Barrat1-2/+8
2024-11-04pnv/xive2: Support for "OS LGS Push" TIMA operationGlenn Miles1-0/+15
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