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2024-05-30hw/intc/arm_gic: Fix writes to GICD_ITARGETSRnSebastian Huber1-0/+7
According to the GICv2 specification section 4.3.12, "Interrupt Processor Targets Registers, GICD_ITARGETSRn": "Any change to a CPU targets field value: [...] * Has an effect on any pending interrupts. This means: - adding a CPU interface to the target list of a pending interrupt makes that interrupt pending on that CPU interface - removing a CPU interface from the target list of a pending interrupt removes the pending state of that interrupt on that CPU interface." Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de> Message-id: 20240524113256.8102-3-sebastian.huber@embedded-brains.de Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30hw/intc/arm_gic: Fix set pending of PPIsSebastian Huber1-1/+4
According to the GICv2 specification section 4.3.7, "Interrupt Set-Pending Registers, GICD_ISPENDRn": "In a multiprocessor implementation, GICD_ISPENDR0 is banked for each connected processor. This register holds the Set-pending bits for interrupts 0-31." Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de> Message-id: 20240524113256.8102-2-sebastian.huber@embedded-brains.de Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28hw/intc/arm_gic: Fix handling of NS view of GICC_APR<n>Andrey Shumilin1-2/+2
In gic_cpu_read() and gic_cpu_write(), we delegate the handling of reading and writing the Non-Secure view of the GICC_APR<n> registers to functions gic_apr_ns_view() and gic_apr_write_ns_view(). Unfortunately we got the order of the arguments wrong, swapping the CPU number and the register number (which the compiler doesn't catch because they're both integers). Most guests probably didn't notice this bug because directly accessing the APR registers is typically something only done by firmware when it is doing state save for going into a sleep mode. Correct the mismatched call arguments. Found by Linux Verification Center (linuxtesting.org) with SVACE. Cc: qemu-stable@nongnu.org Fixes: 51fd06e0ee ("hw/intc/arm_gic: Fix handling of GICC_APR<n>, GICC_NSAPR<n> registers") Signed-off-by: Andrey Shumilin <shum.sdl@nppct.ru> [PMM: Rewrote commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée<alex.bennee@linaro.org>
2024-05-17hw/intc/s390_flic: Fix crash that occurs when saving the machine stateThomas Huth1-1/+1
adapter_info_so_needed() treats its "opaque" parameter as a S390FLICState, but the function belongs to a VMStateDescription that is attached to a TYPE_VIRTIO_CCW_BUS device. This is currently causing a crash when the user tries to save or migrate the VM state. Fix it by using s390_get_flic() to get the correct device here instead. Reported-by: Marc Hartmayer <mhartmay@linux.ibm.com> Fixes: 9d1b0f5bf5 ("s390_flic: add migration-enabled property") Message-ID: <20240517061553.564529-1-thuth@redhat.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Tested-by: Marc Hartmayer <mhartmay@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-05-10i386: select correct components for no-board buildPaolo Bonzini2-1/+30
The local APIC is a part of the CPU and has callbacks that are invoked from multiple accelerators. The IOAPIC on the other hand is optional, but ioapic_eoi_broadcast is used by common x86 code to implement the IOAPIC's implicit EOI mode. Add a stub in case the IOAPIC device is not included but the APIC is. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-ID: <20240509170044.190795-13-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-05-10s390_flic: add migration-enabled propertyPaolo Bonzini1-1/+5
Instead of mucking with css_migration_enabled(), add a property specific to the FLIC device, similar to what is done for TYPE_S390_STATTRIB. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20240509170044.190795-3-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-05-09hw/intc/loongson_ipi: Implement IOCSR address space for MIPSJiaxun Yang1-9/+30
Implement IOCSR address space get functions for MIPS/Loongson CPUs. For MIPS/Loongson without IOCSR (i.e. Loongson-3A1000), get_cpu_iocsr_as will return as null, and send_ipi_data will fail with MEMTX_DECODE_ERROR, which matches expected behavior on hardware. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240508-loongson3-ipi-v1-3-1a7b67704664@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-09hw/intc/loongarch_ipi: Rename as loongson_ipiJiaxun Yang4-5/+352
This device will be shared among LoongArch and MIPS based Loongson machine, rename it as loongson_ipi to reflect this nature. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240508-loongson3-ipi-v1-2-1a7b67704664@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-09hw/intc/loongarch_ipi: Remove pointless MAX_CPU checkJiaxun Yang2-19/+2
Since cpuid will be checked by ipi_getcpu anyway, there is no point to enforce MAX_CPU here. This also saved us from including loongarch board header. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240508-loongson3-ipi-v1-1-1a7b67704664@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-03kvm: move target-dependent interrupt routing out of kvm-all.cPaolo Bonzini1-0/+28
Let hw/hyperv/hyperv.c and hw/intc/s390_flic.c handle (respectively) SynIC and adapter routes, removing the code from target-independent files. This also removes the only occurrence of AdapterInfo outside s390 code, so remove that from typedefs.h. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-04-25hw, target: Add ResetType argument to hold and exit phase methodsPeter Maydell8-12/+12
We pass a ResetType argument to the Resettable class enter phase method, but we don't pass it to hold and exit, even though the callsites have it readily available. This means that if a device cared about the ResetType it would need to record it in the enter phase method to use later on. Pass the type to all three of the phase methods to avoid having to do that. Commit created with for dir in hw target include; do \ spatch --macro-file scripts/cocci-macro-file.h \ --sp-file scripts/coccinelle/reset-type.cocci \ --keep-comments --smpl-spacing --in-place \ --include-headers --dir $dir; done and no manual edits. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20240412160809.1260625-5-peter.maydell@linaro.org
2024-04-25hw/intc/arm_gicv3: Report the VINMI interruptJinjie Ruan1-2/+12
In vCPU Interface, if the vIRQ has the non-maskable property, report vINMI to the corresponding vPE. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-23-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-04-25hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update()Jinjie Ruan1-0/+4
In CPU Interface, if the IRQ has the non-maskable property, report NMI to the corresponding PE. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-22-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-04-25hw/intc/arm_gicv3: Implement NMI interrupt priorityJinjie Ruan3-9/+64
If GICD_CTLR_DS bit is zero and the NMI is non-secure, the NMI priority is higher than 0x80, otherwise it is higher than 0x0. And save the interrupt non-maskable property in hppi.nmi to deliver NMI exception. Since both GICR and GICD can deliver NMI, it is both necessary to check whether the pending irq is NMI in gicv3_redist_update_noirqset and gicv3_update_noirqset. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-21-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-04-25hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read()Peter Maydell3-12/+98
Implement icv_nmiar1_read() for icc_nmiar1_read(), so add definition for ICH_LR_EL2.NMI and ICH_AP1R_EL2.NMI bit. If FEAT_GICv3_NMI is supported, ich_ap_write() should consider ICV_AP1R_EL1.NMI bit. In icv_activate_irq() and icv_eoir_write(), the ICV_AP1R_EL1.NMI bit should be set or clear according to the Non-maskable property. And the RPR priority should also update the NMI bit according to the APR priority NMI bit. By the way, add gicv3_icv_nmiar1_read trace event. If the hpp irq is a NMI, the icv iar read should return 1022 and trap for NMI again Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [PMM: use cs->nmi_support instead of cs->gic->nmi_support] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-20-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-04-25hw/intc/arm_gicv3: Add NMI handling CPU interface registersPeter Maydell3-5/+148
Add the NMIAR CPU interface registers which deal with acknowledging NMI. When introduce NMI interrupt, there are some updates to the semantics for the register ICC_IAR1_EL1 and ICC_HPPIR1_EL1. For ICC_IAR1_EL1 register, it should return 1022 if the intid has non-maskable property. And for ICC_NMIAR1_EL1 register, it should return 1023 if the intid do not have non-maskable property. Howerever, these are not necessary for ICC_HPPIR1_EL1 register. And the APR and RPR has NMI bits which should be handled correctly. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [PMM: Separate out whether cpuif supports NMI from whether the GIC proper (IRI) supports NMI] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-19-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-04-25hw/intc/arm_gicv3: Implement GICD_INMIRJinjie Ruan2-0/+36
Add GICD_INMIR, GICD_INMIRnE register and support access GICD_INMIR0. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-18-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-04-25hw/intc/arm_gicv3_redist: Implement GICR_INMIR0Jinjie Ruan2-0/+20
Add GICR_INMIR0 register and support access GICR_INMIR0. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-17-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-04-25hw/intc/arm_gicv3: Add irq non-maskable propertyJinjie Ruan1-0/+38
A SPI, PPI or SGI interrupt can have non-maskable property. So maintain non-maskable property in PendingIrq and GICR/GICD. Since add new device state, it also needs to be migrated, so also save NMI info in vmstate_gicv3_cpu and vmstate_gicv3. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-16-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-04-25hw/intc/arm_gicv3_kvm: Not set has-nmi=true for the KVM GICv3Jinjie Ruan1-0/+5
So far, there is no FEAT_GICv3_NMI support in the in-kernel GIC, so make it an error to try to set has-nmi=true for the KVM GICv3. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Message-id: 20240407081733.3231820-15-ruanjinjie@huawei.com Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-04-25hw/intc/arm_gicv3: Add has-nmi property to GICv3 deviceJinjie Ruan3-0/+4
Add a property has-nmi to the GICv3 device, and use this to set the NMI bit in the GICD_TYPER register. This isn't visible to guests yet because the property defaults to false and we won't set it in the board code until we've landed all of the changes needed to implement FEAT_GICV3_NMI. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-14-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-04-25hw/intc/arm_gicv3: Add external IRQ lines for NMIJinjie Ruan1-0/+6
Augment the GICv3's QOM device interface by adding one new set of sysbus IRQ line, to signal NMI to each CPU. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-11-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-04-24target/nios2: Remove the deprecated Nios II targetPhilippe Mathieu-Daudé3-317/+0
The Nios II target is deprecated since v8.2 in commit 9997771bc1 ("target/nios2: Deprecate the Nios II architecture"). Remove: - Buildsys / CI infra - User emulation - System emulation (10m50-ghrd & nios2-generic-nommu machines) - Tests Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Marek Vasut <marex@denx.de> Message-Id: <20240327144806.11319-3-philmd@linaro.org>
2024-04-02hw/intc/arm_gicv3: ICC_HPPIR* return SPURIOUS if int group is disabledPeter Maydell1-2/+2
If the group of the highest priority pending interrupt is disabled via ICC_IGRPEN*, the ICC_HPPIR* registers should return INTID_SPURIOUS, not the interrupt ID. (See the GIC architecture specification pseudocode functions ICC_HPPIR1_EL1[] and HighestPriorityPendingInterrupt().) Make HPPIR reads honour the group disable, the way we already do when determining whether to preempt in icc_hppi_can_preempt(). Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240328153333.2522667-1-peter.maydell@linaro.org
2024-03-22hw/intc: Update APLIC IDC after claiming iforce registerFrank Chang1-0/+1
Currently, QEMU only sets the iforce register to 0 and returns early when claiming the iforce register. However, this may leave mip.meip remains at 1 if a spurious external interrupt triggered by iforce register is the only pending interrupt to be claimed, and the interrupt cannot be lowered as expected. This commit fixes this issue by calling riscv_aplic_idc_update() to update the IDC status after the iforce register is claimed. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240321104951.12104-1-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-03-20hw/intc/loongarch_extioi: Fix interrupt routing updateBibo Mao1-1/+1
Interrupt number in loop sentence should be base irq plus loop index, it is missing on checking whether the irq is pending. Fixes: 428a6ef4396 ("Add vmstate post_load support") Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20240313093932.2653518-1-maobibo@loongson.cn>
2024-03-12hw/intc: Check @errp to handle the error of IOAPICCommonClass.realize()Zhao Liu1-0/+4
IOAPICCommonClass implements its own private realize(), and this private realize() allows error. Since IOAPICCommonClass.realize() returns void, to check the error, dereference @errp with ERRP_GUARD(). Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240223085653.1255438-8-zhao1.liu@linux.intel.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-03-09hw/intc/grlib_irqmp: abort realize when ncpus value is out of rangeClément Chigot1-0/+1
Even if the error is set, the build is not aborted when the ncpus value is wrong, the return is missing. Signed-off-by: Clément Chigot <chigot@adacore.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Fixes: 6bf1478543 ("hw/intc/grlib_irqmp: add ncpus property") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240308152719.591232-1-chigot@adacore.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-03-09hw/intc/apic: fix memory leakPaolo Bonzini1-4/+2
deliver_bitmask is allocated on the heap in apic_deliver(), but there are many paths in the function that return before the corresponding g_free() is reached. Fix this by switching to g_autofree and, while at it, also switch to g_new. Do the same in apic_deliver_irq() as well for consistency. Fixes: b5ee0468e9d ("apic: add support for x2APIC mode", 2024-02-14) Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Bui Quang Minh <minhquangbui99@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20240304224133.267640-1-pbonzini@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-03-08hw/intc/riscv_aplic: Fix in_clrip[x] read emulationAnup Patel1-2/+15
The reads to in_clrip[x] registers return rectified input values of the interrupt sources. A rectified input value of an interrupt source is defined by the section "4.5.2 Source configurations (sourcecfg[1]–sourcecfg[1023])" of the RISC-V AIA specification as: "rectified input value = (incoming wire value) XOR (source is inverted)" Update the riscv_aplic_read_input_word() implementation to match the above. Fixes: e8f79343cfc8 ("hw/intc: Add RISC-V AIA APLIC device emulation") Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240306095722.463296-3-apatel@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-03-08hw/intc/riscv_aplic: Fix setipnum_le write emulation for APLIC MSI-modeAnup Patel1-4/+16
The writes to setipnum_le register in APLIC MSI-mode have special consideration for level-triggered interrupts as-per section "4.9.2 Special consideration for level-sensitive interrupt sources" of the RISC-V AIA specification. Particularly, the below text from the RISC-V specification defines the behaviour of writes to setipnum_le for level-triggered interrupts: "A second option is for the interrupt service routine to write the APLIC’s source identity number for the interrupt to the domain’s setipnum register just before exiting. This will cause the interrupt’s pending bit to be set to one again if the source is still asserting an interrupt, but not if the source is not asserting an interrupt." Fix setipnum_le write emulation for APLIC MSI-mode by implementing the above behaviour in riscv_aplic_set_pending() function. Fixes: e8f79343cfc8 ("hw/intc: Add RISC-V AIA APLIC device emulation") Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240306095722.463296-2-apatel@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-03-01hw/intc/Kconfig: Fix GIC settings when using "--without-default-devices"Thomas Huth1-6/+6
When using "--without-default-devices", the ARM_GICV3_TCG and ARM_GIC_KVM settings currently get disabled, though the arm virt machine is only of very limited use in that case. This also causes the migration-test to fail in such builds. Let's make sure that we always keep the GIC switches enabled in the --without-default-devices builds, too. Message-ID: <20240221110059.152665-1-thuth@redhat.com> Tested-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-02-15hw/intc/grlib_irqmp: implements multicore irqClément Chigot1-21/+20
Now there is an ncpus property, use it in order to deliver the IRQ to multiple CPU. Co-developed-by: Frederic Konrad <konrad.frederic@yahoo.fr> Signed-off-by: Clément Chigot <chigot@adacore.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240131085047.18458-5-chigot@adacore.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-15hw/intc/grlib_irqmp: implements the multiprocessor status registerClément Chigot1-3/+32
This implements the multiprocessor status register in grlib-irqmp and bind it to a start signal, which will be later wired in leon3-generic to start a cpu. The EIRQ and BA bits are not implemented. Based on https://gaisler.com/doc/gr712rc-usermanual.pdf, §8.3.5. Co-developed-by: Frederic Konrad <konrad.frederic@yahoo.fr> Signed-off-by: Clément Chigot <chigot@adacore.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240131085047.18458-4-chigot@adacore.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-15hw/intc/grlib_irqmp: add ncpus propertyClément Chigot1-9/+21
This adds a "ncpus" property to the "grlib-irqmp" device to be used later, this required a little refactoring of how we initialize the device (ie: use realize instead of init). Co-developed-by: Frederic Konrad <konrad.frederic@yahoo.fr> Signed-off-by: Clément Chigot <chigot@adacore.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240131085047.18458-3-chigot@adacore.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-15hw/sparc/grlib: split out the headers for each peripheralsClément Chigot1-2/+4
Split out the headers for each peripherals and move them in their right hardware directory. Update Copyright and add SPDX-License-Identifier at the same time. Co-developed-by: Frederic Konrad <konrad.frederic@yahoo.fr> Signed-off-by: Clément Chigot <chigot@adacore.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240131085047.18458-2-chigot@adacore.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-02-14Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Peter Maydell3-108/+402
into staging virtio,pc,pci: features, cleanups, fixes vhost-user-snd support x2APIC mode with TCG support CXL update to r3.1 fixes, cleanups all over the place. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmXMoXUPHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRpFtMIAKUKD0hzJrwOyPo4xsRUMbsB3ehIsJsMKfOK # w+JWzTaojAG8ENPelWBdL2sEIs5U73VOchjLqHbH2m5sz6GJ13214amvdU/fYc8+ # /dU2ZKoAmaR5L1ovKO/fq07y/J6DrITZ5tosy2i84Xa8EnsL4j3wEPNVWsDi7dna # mvXUICSOOoJQ4O2YhSruKCQ8qIgF1/0Oi3u/rcrW3alSs8VQlrtQXxl6k+LbYqek # +Fytco3jMRHPvQ+GYUIwGuHjN15ghArcvbsV0GIa+24BPY5h7YbDYGbfasePT5OK # zDz51jitkoyDrQr+OzwOEe/X5+dVGhayRXfMtU5Qm53IE3y61qc= # =K4b1 # -----END PGP SIGNATURE----- # gpg: Signature made Wed 14 Feb 2024 11:18:13 GMT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (60 commits) MAINTAINERS: Switch to my Enfabrica email virtio-gpu-rutabaga.c: override resource_destroy method virtio-gpu.c: add resource_destroy class method hw/display/virtio-gpu.c: use reset_bh class method hw/smbios: Fix port connector option validation hw/smbios: Fix OEM strings table option validation virtio-gpu: Correct virgl_renderer_resource_get_info() error check hw/cxl: Standardize all references on CXL r3.1 and minor updates hw/cxl: Update mailbox status registers. hw/cxl: Update RAS Capability Definitions for version 3. hw/cxl: Update link register definitions. hw/cxl: Update HDM Decoder capability to version 3 tests/acpi: Update DSDT.cxl to reflect change _STA return value. hw/i386: Fix _STA return value for ACPI0017 tests/acpi: Allow update of DSDT.cxl hw/mem/cxl_type3: Fix potential divide by zero reported by coverity hw/cxl: Pass NULL for a NULL MemoryRegionOps hw/cxl: Pass CXLComponentState to cache_mem_ops hw/cxl/device: read from register values in mdev_reg_read() hw/cxl/mbox: Remove dead code ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-02-14hw/i386/x86: Fix PIC interrupt handling if APIC is globally disabledBernhard Beschow1-0/+13
QEMU populates the apic_state attribute of x86 CPUs if supported by real hardware or if SMP is active. When handling interrupts, it just checks whether apic_state is populated to route the interrupt to the PIC or to the APIC. However, chapter 10.4.3 of [1] requires that: When IA32_APIC_BASE[11] is 0, the processor is functionally equivalent to an IA-32 processor without an on-chip APIC. This means that when apic_state is populated, QEMU needs to check for the MSR_IA32_APICBASE_ENABLE flag in addition. Implement this which fixes some real-world BIOSes. [1] Intel 64 and IA-32 Architectures Software Developer's Manual, Vol. 3A: System Programming Guide, Part 1 Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20240106132546.21248-3-shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2024-02-14apic, i386/tcg: add x2apic transitionsBui Quang Minh2-8/+67
This commit adds support for x2APIC transitions when writing to MSR_IA32_APICBASE register and finally adds CPUID_EXT_X2APIC to TCG_EXT_FEATURES. The set_base in APICCommonClass now returns an integer to indicate error in execution. apic_set_base return -1 on invalid APIC state transition, accelerator can use this to raise appropriate exception. Signed-off-by: Bui Quang Minh <minhquangbui99@gmail.com> Message-Id: <20240111154404.5333-4-minhquangbui99@gmail.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2024-02-14apic: add support for x2APIC modeBui Quang Minh2-68/+228
This commit extends the APIC ID to 32-bit long and remove the 255 max APIC ID limit in userspace APIC. The array that manages local APICs is now dynamically allocated based on the max APIC ID of created x86 machine. Also, new x2APIC IPI destination determination scheme, self IPI and x2APIC mode register access are supported. Signed-off-by: Bui Quang Minh <minhquangbui99@gmail.com> Message-Id: <20240111154404.5333-3-minhquangbui99@gmail.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2024-02-14i386/tcg: implement x2APIC registers MSR accessBui Quang Minh2-32/+94
This commit creates apic_register_read/write which are used by both apic_mem_read/write for MMIO access and apic_msr_read/write for MSR access. The apic_msr_read/write returns -1 on error, accelerator can use this to raise the appropriate exception. Signed-off-by: Bui Quang Minh <minhquangbui99@gmail.com> Message-Id: <20240111154404.5333-2-minhquangbui99@gmail.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2024-02-13hw/intc/s390_flic: Consolidate the use of device_class_set_parent_realize()Zhao Liu1-2/+3
Use device_class_set_parent_realize() to set parent realize() directly. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-01-30hw/intc/xics: Include missing 'cpu.h' headerPhilippe Mathieu-Daudé1-0/+1
Include missing headers in order to avoid when refactoring unrelated headers: hw/intc/xics.c: In function 'icp_realize': hw/intc/xics.c:304:5: error: unknown type name 'PowerPCCPU' 304 | PowerPCCPU *cpu; | ^~~~~~~~~~ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-01-11Merge tag 'pull-loongarch-20240111' of https://gitlab.com/gaosong/qemu into ↵Peter Maydell2-154/+267
staging pull-loongarch-20240111 # -----BEGIN PGP SIGNATURE----- # # iLMEAAEKAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZZ/QKgAKCRBAov/yOSY+ # 34eqBADA48++Z9gETFNheLUHdYEaja2emn+gSaoHLFquyq/l53w8RfrUII+BzV1o # T7D8xjlVQldAYZzqQn2pQe2S7r4ggfeNmxGxwJbCTW9sooGMwBnU8+Ix3ruSet7K # gI+UHLU4oHk6jdrT384tux2EG+qUmlLN1c7j4G/z1OzKEwFv7Q== # =+Pi0 # -----END PGP SIGNATURE----- # gpg: Signature made Thu 11 Jan 2024 11:25:30 GMT # gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF # gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF * tag 'pull-loongarch-20240111' of https://gitlab.com/gaosong/qemu: hw/intc/loongarch_extioi: Add vmstate post_load support hw/intc/loongarch_extioi: Add dynamic cpu number support hw/loongarch/virt: Set iocsr address space per-board rather than percpu hw/intc/loongarch_ipi: Use MemTxAttrs interface for ipi ops target/loongarch: Add loongarch kvm into meson build target/loongarch: Implement set vcpu intr for kvm target/loongarch: Restrict TCG-specific code target/loongarch: Implement kvm_arch_handle_exit target/loongarch: Implement kvm_arch_init_vcpu target/loongarch: Implement kvm_arch_init function target/loongarch: Implement kvm get/set registers target/loongarch: Supplement vcpu env initial when vcpu reset target/loongarch: Define some kvm_arch interfaces linux-headers: Synchronize linux headers from linux v6.7.0-rc8 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-01-11hw/intc/loongarch_extioi: Add vmstate post_load supportBibo Mao1-44/+76
There are elements sw_ipmap and sw_coremap, which is usd to speed up irq injection flow. They are saved and restored in vmstate during migration, indeed they can calculated from hw registers. Here post_load is added for get sw_ipmap and sw_coremap from extioi hw state. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20231215100333.3933632-5-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2024-01-11hw/intc/loongarch_extioi: Add dynamic cpu number supportBibo Mao1-36/+71
On LoongArch physical machine, one extioi interrupt controller only supports 4 cpus. With processor more than 4 cpus, there are multiple extioi interrupt controllers; if interrupts need to be routed to other cpus, they are forwarded from extioi node0 to other extioi nodes. On virt machine model, there is simple extioi interrupt device model. All cpus can access register of extioi interrupt controller, however interrupt can only be route to 4 vcpu for compatible with old kernel. This patch adds dynamic cpu number support about extioi interrupt. With old kernel legacy extioi model is used, however kernel can detect and choose new route method in future, so that interrupt can be routed to all vcpus. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20231215100333.3933632-4-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2024-01-11hw/loongarch/virt: Set iocsr address space per-board rather than percpuBibo Mao2-18/+46
LoongArch system has iocsr address space, most iocsr registers are per-board, however some iocsr register spaces banked for percpu such as ipi mailbox and extioi interrupt status. For banked iocsr space, each cpu has the same iocsr space, but separate data. This patch changes iocsr address space per-board rather percpu, for iocsr registers specified for cpu, MemTxAttrs.requester_id can be parsed for the cpu. With this patches, the total address space on board will be simple, only iocsr address space and system memory, rather than the number of cpu and system memory. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20231215100333.3933632-3-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2024-01-11hw/intc/loongarch_ipi: Use MemTxAttrs interface for ipi opsBibo Mao1-59/+77
There are two interface pairs for MemoryRegionOps, read/write and read_with_attrs/write_with_attrs. The later is better for ipi device emulation since initial cpu can be parsed from attrs.requester_id. And requester_id can be overrided for IOCSR_IPI_SEND and mail_send function when it is to forward message to another vcpu. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20231215100333.3933632-2-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2024-01-09hw/intc/arm_gicv3_cpuif: Mark up VNCR offsets for GIC CPU registersPeter Maydell1-0/+11
Mark up the cpreginfo structs for the GIC CPU registers to indicate the offsets from VNCR_EL2, as defined in table D8-66 in rule R_CSRPQ in the Arm ARM. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Miguel Luis <miguel.luis@oracle.com>
2024-01-09hw/intc/arm_gicv3_cpuif: handle LPIs in in the list registersPeter Maydell1-4/+13
The hypervisor can deliver (virtual) LPIs to a guest by setting up a list register to have an intid which is an LPI. The GIC has to treat these a little differently to standard interrupt IDs, because LPIs have no Active state, and so the guest will only EOI them, it will not also deactivate them. So icv_eoir_write() must do two things: * if the LPI ID is not in any list register, we drop the priority but do not increment the EOI count * if the LPI ID is in a list register, we immediately deactivate it, regardless of the split-drop-and-deactivate control This can be seen in the VirtualWriteEOIR0() and VirtualWriteEOIR1() pseudocode in the GICv3 architecture specification. Without this fix, potentially a hypervisor guest might stall because LPIs get stuck in a bogus Active+Pending state. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Miguel Luis <miguel.luis@oracle.com>
generated by cgit v1.1 at 2025-09-21 05:30:24 +0000