| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2023-02-27 | hw/intc/i8259: Document i8259_init() | Philippe Mathieu-Daudé | 1 | -2/+2 |
| 2023-02-27 | hw: Move ioapic*.h to intc/ | Bernhard Beschow | 4 | -5/+123 |
| 2023-02-27 | hw/intc/armv7m_nvic: Use QOM cast CPU() macro | Philippe Mathieu-Daudé | 1 | -3/+3 |
| 2023-02-27 | target/arm: Wrap arm_rebuild_hflags calls with tcg_enabled | Fabiano Rosas | 1 | -7/+13 |
| 2023-02-16 | target/arm: Store CPUARMState::nvic as NVICState* | Philippe Mathieu-Daudé | 1 | -25/+13 |
| 2023-02-03 | target/arm: Mark up sysregs for HFGRTR bits 36..63 | Peter Maydell | 1 | -0/+2 |
| 2023-02-03 | hvf: arm: Add support for GICv3 | Alexander Graf | 1 | -1/+15 |
| 2023-01-20 | Merge tag 'pull-include-2023-01-20' of https://repo.or.cz/qemu/armbru into st... | Peter Maydell | 2 | -0/+2 |
| 2023-01-20 | include/hw/ppc: Split pnv_chip.h off pnv.h | Markus Armbruster | 2 | -0/+2 |
| 2023-01-19 | Merge tag 'trivial-branch-for-8.0-pull-request' of https://gitlab.com/laurent... | Peter Maydell | 1 | -6/+6 |
| 2023-01-18 | bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx | Philippe Mathieu-Daudé | 4 | -20/+20 |
| 2023-01-16 | hw/intc: Mark more interrupt-controller files as target independent | Thomas Huth | 1 | -4/+4 |
| 2023-01-16 | hw/intc: Move some files out of the target-specific source set | Philippe Mathieu-Daudé | 1 | -2/+2 |
| 2023-01-16 | Merge tag 'mips-20230113' of https://github.com/philmd/qemu into staging | Peter Maydell | 6 | -40/+68 |
| 2023-01-13 | hw/intc: Extract the IRQ counting functions into a separate file | Thomas Huth | 5 | -33/+64 |
| 2023-01-13 | hw/intc/i8259: Make using the isa_pic singleton more type-safe | Bernhard Beschow | 1 | -7/+4 |
| 2023-01-12 | hw/intc/xilinx_intc: Use 'XpsIntc' typedef instead of 'struct xlx_pic' | Philippe Mathieu-Daudé | 1 | -15/+13 |
| 2023-01-12 | hw/intc/omap_intc: Use CamelCase for TYPE_OMAP_INTC type name | Philippe Mathieu-Daudé | 1 | -19/+19 |
| 2023-01-12 | hw/arm/omap: Drop useless casts from void * to pointer | Philippe Mathieu-Daudé | 1 | -6/+6 |
| 2023-01-07 | Merge tag 'pull-loongarch-20230106' of https://gitlab.com/gaosong/qemu into s... | Peter Maydell | 2 | -7/+57 |
| 2023-01-06 | hw/intc/loongarch_pch: Change default irq number of pch irq controller | Tianrui Zhao | 1 | -1/+2 |
| 2023-01-06 | hw/intc/loongarch_pch_pic: add irq number property | Tianrui Zhao | 1 | -4/+30 |
| 2023-01-06 | hw/intc/loongarch_pch_msi: add irq number property | Tianrui Zhao | 1 | -3/+26 |
| 2023-01-06 | hw/intc: sifive_plic: Fix the pending register range check | Bin Meng | 1 | -2/+3 |
| 2023-01-06 | hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 | Bin Meng | 1 | -2/+3 |
| 2023-01-06 | hw/intc: sifive_plic: Update "num-sources" property default value | Bin Meng | 1 | -1/+7 |
| 2023-01-06 | hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in ... | Bin Meng | 1 | -3/+4 |
| 2023-01-06 | hw/intc: sifive_plic: Improve robustness of the PLIC config parser | Bin Meng | 1 | -8/+16 |
| 2023-01-06 | hw/intc: sifive_plic: Drop PLICMode_H | Bin Meng | 1 | -1/+0 |
| 2023-01-06 | hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers | Bin Meng | 1 | -0/+2 |
| 2023-01-06 | hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC | Bin Meng | 1 | -0/+1 |
| 2023-01-06 | hw/intc: sifive_plic: fix out-of-bound access of source_priority array | Jim Shu | 1 | -1/+11 |
| 2023-01-06 | hw/intc: sifive_plic: Renumber the S irqs for numa support | Frédéric Pétrot | 1 | -2/+2 |
| 2022-12-16 | hw/intc/xics: Convert TYPE_ICS to 3-phase reset | Peter Maydell | 1 | -4/+5 |
| 2022-12-16 | hw/intc/xics: Reset TYPE_ICS objects with device_cold_reset() | Peter Maydell | 1 | -1/+1 |
| 2022-12-15 | hw/intc: Convert TYPE_KVM_ARM_ITS to 3-phase reset | Peter Maydell | 1 | -5/+9 |
| 2022-12-15 | hw/intc: Convert TYPE_ARM_GICV3_ITS to 3-phase reset | Peter Maydell | 1 | -5/+9 |
| 2022-12-15 | hw/intc: Convert TYPE_ARM_GICV3_ITS_COMMON to 3-phase reset | Peter Maydell | 1 | -3/+4 |
| 2022-12-15 | hw/intc: Convert TYPE_KVM_ARM_GICV3 to 3-phase reset | Peter Maydell | 1 | -5/+9 |
| 2022-12-15 | hw/intc: Convert TYPE_ARM_GICV3_COMMON to 3-phase reset | Peter Maydell | 1 | -3/+4 |
| 2022-12-15 | hw/intc: Convert TYPE_ARM_GIC_KVM to 3-phase reset | Peter Maydell | 1 | -5/+9 |
| 2022-12-15 | hw/intc: Convert TYPE_ARM_GIC_COMMON to 3-phase reset | Peter Maydell | 1 | -3/+4 |
| 2022-12-15 | hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement | Luke Starrett | 1 | -2/+2 |
| 2022-11-21 | hw/intc: add implementation of GICD_IIDR to Arm GIC | Alex Bennée | 1 | -1/+11 |
| 2022-11-21 | hw/intc: clean-up access to GIC multi-byte registers | Alex Bennée | 1 | -6/+10 |
| 2022-11-14 | hw/intc/arm_gicv3: fix prio masking on pmr write | Jens Wiklander | 1 | -2/+1 |
| 2022-11-04 | hw/intc: Fix LoongArch extioi coreisr accessing | Xiaojuan Yang | 1 | -4/+6 |
| 2022-11-04 | hw/intc: Convert the memops to with_attrs in LoongArch extioi | Xiaojuan Yang | 2 | -16/+18 |
| 2022-10-31 | hw/ppc/mac.h: Rename to include/hw/nvram/mac_nvram.h | BALATON Zoltan | 2 | -2/+0 |
| 2022-10-17 | hw/intc: Fix LoongArch ipi device emulation | Xiaojuan Yang | 1 | -1/+0 |
