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AgeCommit message (Expand)AuthorFilesLines
2022-04-06Remove qemu-common.h include from most unitsMarc-André Lureau1-1/+0
2022-04-06Replace qemu_real_host_page variables with inlined functionsMarc-André Lureau1-1/+1
2022-03-25hw/intc/arm_gicv3_its: Add missing newlines to process_mapc() loggingPeter Maydell1-2/+2
2022-03-21Use g_new() & friends where that makes obvious senseMarkus Armbruster2-4/+4
2022-03-18hw/intc: Rename CONFIG_ARM_GIC_TCG into CONFIG_ARM_GICV3_TCGEric Auger2-3/+3
2022-03-14ppc/xive2: Make type Xive2EndSource not user creatableCédric Le Goater1-0/+1
2022-03-07hw/intc/arm_gicv3_cpuif: Fix register names in ICV_HPPIR read trace eventPeter Maydell1-1/+2
2022-03-07hw/intc/arm_gicv3: Fix missing spaces in error log messagesPeter Maydell2-4/+4
2022-03-07hw/intc/arm_gicv3: Specify valid and impl in MemoryRegionOpsPeter Maydell1-0/+8
2022-03-07hw/intc/arm_gicv3_its: Add trace events for table reads and writesPeter Maydell2-6/+40
2022-03-07hw/intc/arm_gicv3_its: Add trace events for commandsPeter Maydell2-2/+38
2022-03-03hw/intc: Add RISC-V AIA IMSIC device emulationAnup Patel3-0/+452
2022-03-02pnv/xive2: Add support for 8bits thread idCédric Le Goater2-1/+7
2022-03-02pnv/xive2: Add support for automatic save&restoreCédric Le Goater3-6/+141
2022-03-02xive2: Add a get_config() handler for the router configurationCédric Le Goater2-0/+20
2022-03-02pnv/xive2: Add support XIVE2 P9-compat mode (or Gen1)Cédric Le Goater2-5/+23
2022-03-02ppc/pnv: add XIVE Gen2 TIMA supportCédric Le Goater2-2/+120
2022-03-02pnv/xive2: Introduce new capability bitsCédric Le Goater2-2/+7
2022-03-02ppc/pnv: Add support for PQ offload on PHB5Cédric Le Goater1-1/+21
2022-03-02ppc/xive: Add support for PQ state bits offloadCédric Le Goater5-14/+175
2022-03-02ppc/xive2: Add support for notification injection on ESB pagesCédric Le Goater2-0/+19
2022-03-02ppc/pnv: Add a XIVE2 controller to the POWER10 chipCédric Le Goater3-1/+2457
2022-03-02ppc/xive2: Introduce a presenter matching routineCédric Le Goater1-0/+82
2022-03-02ppc/xive2: Introduce a XIVE2 core frameworkCédric Le Goater2-1/+668
2022-02-21Mark remaining global TypeInfo instances as constBernhard Beschow2-2/+2
2022-02-16hw/intc: Add RISC-V AIA APLIC device emulationAnup Patel3-0/+982
2022-02-08hw/intc/arm_gicv3_its: Split error checksPeter Maydell1-21/+31
2022-02-08hw/intc/arm_gicv3_its: Don't allow intid 1023 in MAPI/MAPTIPeter Maydell1-2/+1
2022-02-08hw/intc/arm_gicv3_its: In MAPC with V=0, don't check rdbase fieldPeter Maydell1-12/+12
2022-02-08hw/intc/arm_gicv3_its: Drop TableDesc and CmdQDesc valid fieldsPeter Maydell1-17/+14
2022-02-08hw/intc/arm_gicv3_its: Make update_ite() use ITEntryPeter Maydell1-30/+32
2022-02-08hw/intc/arm_gicv3_its: Pass ITE values back from get_ite() via a structPeter Maydell1-47/+55
2022-02-08hw/intc/arm_gicv3_its: Avoid nested ifs in get_ite()Peter Maydell1-13/+15
2022-02-08hw/intc/arm_gicv3_its: Fix address calculation in get_ite() and update_ite()Peter Maydell2-26/+21
2022-02-08hw/intc/arm_gicv3_its: Pass CTEntry to update_cte()Peter Maydell1-15/+17
2022-02-08hw/intc/arm_gicv3_its: Keep CTEs as a struct, not a raw uint64_tPeter Maydell1-44/+52
2022-02-08hw/intc/arm_gicv3_its: Pass DTEntry to update_dte()Peter Maydell1-17/+18
2022-02-08hw/intc/arm_gicv3_its: Keep DTEs as a struct, not a raw uint64_tPeter Maydell1-55/+56
2022-02-08hw/intc/arm_gicv3_its: Use address_space_map() to access command queue packetsPeter Maydell2-149/+61
2022-01-31Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220130' into s...Peter Maydell1-4/+18
2022-01-28Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20220128'...Peter Maydell6-26/+408
2022-01-28hw/intc/arm_gicv3_its: Implement MOVIPeter Maydell3-0/+215
2022-01-28hw/intc/arm_gicv3_its: Implement MOVALLPeter Maydell3-0/+125
2022-01-28hw/intc/arm_gicv3_its: Check table bounds against correct limitPeter Maydell1-9/+9
2022-01-28hw/intc/arm_gicv3_its: Make GITS_BASER<n> RAZ/WI for unimplemented registersPeter Maydell1-0/+8
2022-01-28hw/intc/arm_gicv3_its: Provide read accessor for translation_opsPeter Maydell1-0/+13
2022-01-28hw/intc/arm_gicv3: Set GICR_CTLR.CES if LPIs are supportedPeter Maydell2-0/+5
2022-01-28hw/intc/arm_gicv3_redist: Remove unnecessary zero checksPeter Maydell1-5/+3
2022-01-28hw/intc/arm_gicv3_its: Sort ITS command list into numeric orderPeter Maydell1-5/+5
2022-01-28hw/intc/arm_gicv3: Honour GICD_CTLR.EnableGrp1NS for LPIsPeter Maydell1-0/+1
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