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2023-11-03Merge tag 'migration-20231102-pull-request' of https://gitlab.com/juan.quinte...Stefan Hajnoczi1-2/+16
2023-11-01migration: Hack to maintain backwards compatibility for ppcJuan Quintela1-2/+16
2023-11-01hw/m68k/irqc: Pass CPU using QOM link propertyPhilippe Mathieu-Daudé1-1/+9
2023-10-27target/arm: Move feature test functions to their own headerPeter Maydell1-0/+1
2023-10-25kvm: require KVM_IRQFD for kernel irqchipPaolo Bonzini1-1/+1
2023-10-25kvm: require KVM_CAP_SIGNAL_MSIPaolo Bonzini1-2/+1
2023-10-20Merge tag 'migration-20231020-pull-request' of https://gitlab.com/juan.quinte...Stefan Hajnoczi3-6/+3
2023-10-20migration: simplify blockersSteve Sistare3-6/+3
2023-10-19hw/intc/spapr_xive: Do not use SysBus API to map local MMIO regionPhilippe Mathieu-Daudé1-6/+6
2023-10-19hw/intc/spapr_xive: Move sysbus_init_mmio() calls aroundPhilippe Mathieu-Daudé1-3/+3
2023-10-19hw/intc/apic: Use ERRP_GUARD() in apic_common_realize()Philippe Mathieu-Daudé1-0/+4
2023-10-12target/riscv: move KVM only files to kvm subdirDaniel Henrique Barboza1-1/+1
2023-10-04accel/tcg: Replace CPUState.env_ptr with cpu_env()Richard Henderson3-8/+8
2023-09-29hw/intc/arm_gicv3_its: Avoid shadowing variable in do_process_its_cmd()Peter Maydell1-3/+3
2023-09-29hw/intc/openpic: Clean up local variable shadowingPhilippe Mathieu-Daudé1-5/+2
2023-09-21hw/other: spelling fixesMichael Tokarev8-12/+12
2023-09-18ppc/xive: Fix uint32_t overflowCédric Le Goater1-1/+1
2023-09-11Merge tag 'pull-riscv-to-apply-20230911' of https://github.com/alistair23/qem...Stefan Hajnoczi3-25/+63
2023-09-11hw/intc/riscv_aplic.c fix non-KVM --enable-debug buildDaniel Henrique Barboza1-6/+2
2023-09-11target/riscv: update APLIC and IMSIC to support KVM AIAYong-Xuan Wang2-20/+61
2023-09-11hw/intc: Make rtc variable names consistentJason Chien1-3/+3
2023-09-11hw/intc: Fix upper/lower mtime write calculationJason Chien1-2/+3
2023-09-08hw/intc/arm_gicv3_its: Avoid maybe-uninitialized error in get_vte()Philippe Mathieu-Daudé1-9/+6
2023-09-06ppc/xive: Add support for the PC MMIOsCédric Le Goater1-36/+48
2023-09-06ppc/xive: Handle END triggers between chips with MMIOsCédric Le Goater2-2/+68
2023-09-06ppc/xive: Introduce a new XiveRouter end_notify() handlerCédric Le Goater1-10/+18
2023-09-06ppc/xive: Use address_space routines to access the machine RAMCédric Le Goater2-8/+46
2023-08-31accel: Remove HAX acceleratorPhilippe Mathieu-Daudé1-2/+1
2023-08-24hw/intc/loongarch_pch: fix edge triggered irq handlingBibo Mao1-1/+6
2023-07-25arm: spelling fixesMichael Tokarev3-4/+4
2023-07-25s390x: spelling fixesMichael Tokarev1-1/+1
2023-07-18s390x: Fix QEMU abort by selecting S390_FLIC_KVMCédric Le Goater1-1/+0
2023-07-07pnv/xive2: Always pass a presenter object when accessing the TIMAFrederic Barrat1-2/+4
2023-07-07pnv/xive: Print CPU target in all TIMA tracesFrederic Barrat2-4/+4
2023-07-07pnv/xive: Allow mmio operations of any size on the ESB CI pagesFrederic Barrat2-6/+6
2023-07-07pnv/xive: Add property on xive sources to define PQ state on resetFrederic Barrat1-2/+6
2023-07-07pnv/xive2: Fix TIMA offset for indirect accessFrederic Barrat1-2/+18
2023-07-07pnv/xive2: Allow indirect TIMA accesses of all sizesFrederic Barrat1-2/+2
2023-06-28hw/intc/arm_gic: Rename 'first_cpu' argumentPhilippe Mathieu-Daudé1-2/+2
2023-06-28hw/intc/arm_gic: Un-inline GIC*/ITS class_name() helpersPhilippe Mathieu-Daudé3-0/+33
2023-06-25pnv/xive2: Check TIMA special ops against a dedicated array for P10Frederic Barrat2-41/+43
2023-06-25pnv/xive2: Add a get_config() method on the presenter classFrederic Barrat4-0/+46
2023-06-20meson: Replace softmmu_ss -> system_ssPhilippe Mathieu-Daudé1-22/+22
2023-06-19hw/intc/allwinner-a10-pic: Handle IRQ levels other than 0 or 1Peter Maydell1-1/+1
2023-06-16hw/intc: Set physical cpuid route for LoongArch ipi deviceTianrui Zhao1-7/+37
2023-06-14hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only.Tommy Wu1-2/+2
2023-06-10pnv/xive2: Quiet down some error messagesFrederic Barrat1-0/+4
2023-06-10pnv/xive2: Handle TIMA access through all portsFrederic Barrat2-1/+5
2023-06-10pnv/xive2: Introduce macros to manipulate TIMA addressesFrederic Barrat1-7/+7
2023-06-10pnv/xive2: Allow writes to the Physical Thread Enable registersFrederic Barrat1-0/+1
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