| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2022-06-28 | Trivial: 3 char repeat typos | Dr. David Alan Gilbert | 1 | -1/+1 |
| 2022-06-20 | pnv/xive2: Access direct mapped thread contexts from all chips | Frederic Barrat | 1 | -4/+14 |
| 2022-06-10 | hw/intc: sifive_plic: Avoid overflowing the addr_config buffer | Alistair Francis | 1 | -10/+9 |
| 2022-06-08 | Fix 'writeable' typos | Peter Maydell | 5 | -6/+6 |
| 2022-06-06 | hw/intc: Add LoongArch extioi interrupt controller(EIOINTC) | Xiaojuan Yang | 4 | -0/+322 |
| 2022-06-06 | hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI) | Xiaojuan Yang | 4 | -0/+82 |
| 2022-06-06 | hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC) | Xiaojuan Yang | 4 | -0/+445 |
| 2022-06-06 | hw/loongarch: Add LoongArch ipi interrupt support(IPI) | Xiaojuan Yang | 4 | -0/+250 |
| 2022-05-26 | pnv/xive2: Don't overwrite PC registers when writing TCTXT registers | Frederic Barrat | 1 | -3/+0 |
| 2022-05-24 | hw/intc: Pass correct hartid while updating mtimecmp | Atish Patra | 1 | -1/+2 |
| 2022-05-19 | hw/intc/arm_gicv3: Provide ich_num_aprs() | Peter Maydell | 1 | -6/+10 |
| 2022-05-19 | hw/intc/arm_gicv3: Use correct number of priority bits for the CPU | Peter Maydell | 2 | -4/+16 |
| 2022-05-19 | hw/intc/arm_gicv3: Support configurable number of physical priority bits | Peter Maydell | 1 | -54/+128 |
| 2022-05-19 | hw/intc/arm_gicv3_kvm.c: Stop using GIC_MIN_BPR constant | Peter Maydell | 1 | -3/+13 |
| 2022-05-19 | hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1 | Peter Maydell | 1 | -1/+1 |
| 2022-05-19 | hw/intc/arm_gicv3_cpuif: Handle CPUs that don't specify GICv3 parameters | Peter Maydell | 1 | -5/+13 |
| 2022-05-05 | ppc/xive: Update the state of the External interrupt signal | Frederic Barrat | 2 | -0/+16 |
| 2022-05-05 | ppc/xive: Always recompute the PIPR when pushing an OS context | Frederic Barrat | 2 | -10/+17 |
| 2022-05-05 | target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h | Richard Henderson | 2 | -6/+0 |
| 2022-05-05 | target/arm: Split out cpregs.h | Richard Henderson | 2 | -0/+3 |
| 2022-04-26 | hw/intc: Vectored Interrupt Controller (VIC) | Amir Gonnen | 3 | -0/+317 |
| 2022-04-22 | Merge tag 'pull-target-arm-20220422-1' of https://git.linaro.org/people/pmayd... | Richard Henderson | 9 | -242/+1508 |
| 2022-04-22 | hw/intc/arm_gicv3: Allow 'revision' property to be set to 4 | Peter Maydell | 2 | -5/+12 |
| 2022-04-22 | hw/intc/arm_gicv3: Update ID and feature registers for GICv4 | Peter Maydell | 6 | -12/+32 |
| 2022-04-22 | hw/intc/arm_gicv3_redist: Implement gicv3_redist_inv_vlpi() | Peter Maydell | 1 | -2/+5 |
| 2022-04-22 | hw/intc/arm_gicv3_redist: Implement gicv3_redist_vinvall() | Peter Maydell | 1 | -1/+7 |
| 2022-04-22 | hw/intc/arm_gicv3_redist: Implement gicv3_redist_mov_vlpi() | Peter Maydell | 1 | -2/+18 |
| 2022-04-22 | hw/intc/arm_gicv3_redist: Use set_pending_table_bit() in mov handling | Peter Maydell | 1 | -8/+1 |
| 2022-04-22 | hw/intc/arm_gicv3_redist: Implement gicv3_redist_vlpi_pending() | Peter Maydell | 1 | -2/+21 |
| 2022-04-22 | hw/intc/arm_gicv3_redist: Implement gicv3_redist_process_vlpi() | Peter Maydell | 1 | -4/+44 |
| 2022-04-22 | hw/intc/arm_gicv3_redist: Factor out "update bit in pending table" code | Peter Maydell | 1 | -19/+30 |
| 2022-04-22 | hw/intc/arm_gicv3_redist: Recalculate hppvlpi on VPENDBASER writes | Peter Maydell | 1 | -3/+84 |
| 2022-04-22 | hw/intc/arm_gicv3_redist: Factor out "update hpplpi for all LPIs" logic | Peter Maydell | 1 | -20/+46 |
| 2022-04-22 | hw/intc/arm_gicv3_redist: Factor out "update hpplpi for one LPI" logic | Peter Maydell | 1 | -27/+47 |
| 2022-04-22 | hw/intc/arm_gicv3_cpuif: Don't recalculate maintenance irq unnecessarily | Peter Maydell | 1 | -5/+5 |
| 2022-04-22 | hw/intc/arm_gicv3_cpuif: Support vLPIs | Peter Maydell | 5 | -6/+137 |
| 2022-04-22 | hw/intc/arm_gicv3_cpuif: Split "update vIRQ/vFIQ" from gicv3_cpuif_virt_update() | Peter Maydell | 3 | -25/+53 |
| 2022-04-22 | hw/intc/arm_gicv3: Implement new GICv4 redistributor registers | Peter Maydell | 3 | -0/+99 |
| 2022-04-22 | hw/intc/arm_gicv3: Implement GICv4's new redistributor frame | Peter Maydell | 3 | -5/+26 |
| 2022-04-22 | hw/intc/arm_gicv3_its: Implement VINVALL | Peter Maydell | 4 | -0/+45 |
| 2022-04-22 | hw/intc/arm_gicv3_its: Implement VMOVI | Peter Maydell | 4 | -0/+116 |
| 2022-04-22 | hw/intc/arm_gicv3_its: Implement INV for virtual interrupts | Peter Maydell | 3 | -2/+31 |
| 2022-04-22 | hw/intc/arm_gicv3_its: Implement INV command properly | Peter Maydell | 4 | -2/+74 |
| 2022-04-22 | hw/intc/arm_gicv3_its: Implement VSYNC | Peter Maydell | 3 | -0/+13 |
| 2022-04-22 | hw/intc/arm_gicv3_its: Implement VMOVP | Peter Maydell | 3 | -0/+85 |
| 2022-04-22 | hw/intc/arm_gicv3: Keep pointers to every connected ITS | Peter Maydell | 3 | -0/+6 |
| 2022-04-22 | hw/intc/arm_gicv3_its: Handle virtual interrupts in process_its_cmd() | Peter Maydell | 4 | -2/+125 |
| 2022-04-22 | hw/intc/arm_gicv3_its: Split out process_its_cmd() physical interrupt code | Peter Maydell | 1 | -17/+32 |
| 2022-04-22 | hw/intc/arm_gicv3_its: Factor out CTE lookup sequence | Peter Maydell | 1 | -70/+39 |
| 2022-04-22 | hw/intc/arm_gicv3_its: Factor out "find ITE given devid, eventid" | Peter Maydell | 1 | -50/+54 |
