riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-12-29	hw/intc: Constify VMState	Richard Henderson	1	-1/+1
2023-10-04	accel/tcg: Replace CPUState.env_ptr with cpu_env()	Richard Henderson	1	-6/+6
2023-09-11	hw/intc: Make rtc variable names consistent	Jason Chien	1	-3/+3
2023-09-11	hw/intc: Fix upper/lower mtime write calculation	Jason Chien	1	-2/+3
2023-03-05	hw: intc: Use cpu_by_arch_id to fetch CPU state	Mayuresh Chitale	1	-8/+8
2022-09-07	hw/intc: Move mtimer/mtimecmp to aclint	Atish Patra	1	-14/+34
2022-06-08	Fix 'writeable' typos	Peter Maydell	1	-1/+1
2022-05-24	hw/intc: Pass correct hartid while updating mtimecmp	Atish Patra	1	-1/+2
2022-04-22	hw/intc: riscv_aclint: Add reset function of ACLINT devices	Jim Shu	1	-0/+39
2022-04-22	hw/intc: Make RISC-V ACLINT mtime MMIO register writable	Frank Chang	1	-21/+50
2022-04-22	hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINT	Frank Chang	1	-15/+27
2022-04-22	hw/intc: Add .impl.[min\|max]_access_size declaration in RISC-V ACLINT	Frank Chang	1	-0/+4
2022-03-21	Use g_new() & friends where that makes obvious sense	Markus Armbruster	1	-3/+3
2021-09-21	hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT	Anup Patel	1	-114/+259
2021-09-21	hw/intc: Rename sifive_clint sources to riscv_aclint sources	Anup Patel	1	-0/+315