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path: root/hw/intc/gicv3_internal.h
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2022-04-22hw/intc/arm_gicv3: Update ID and feature registers for GICv4Peter Maydell1-4/+11
2022-04-22hw/intc/arm_gicv3_cpuif: Support vLPIsPeter Maydell1-0/+13
2022-04-22hw/intc/arm_gicv3_cpuif: Split "update vIRQ/vFIQ" from gicv3_cpuif_virt_update()Peter Maydell1-0/+11
2022-04-22hw/intc/arm_gicv3: Implement new GICv4 redistributor registersPeter Maydell1-0/+21
2022-04-22hw/intc/arm_gicv3: Implement GICv4's new redistributor framePeter Maydell1-0/+21
2022-04-22hw/intc/arm_gicv3_its: Implement VINVALLPeter Maydell1-0/+13
2022-04-22hw/intc/arm_gicv3_its: Implement VMOVIPeter Maydell1-0/+23
2022-04-22hw/intc/arm_gicv3_its: Implement INV for virtual interruptsPeter Maydell1-0/+9
2022-04-22hw/intc/arm_gicv3_its: Implement INV command properlyPeter Maydell1-0/+12
2022-04-22hw/intc/arm_gicv3_its: Implement VSYNCPeter Maydell1-0/+1
2022-04-22hw/intc/arm_gicv3_its: Implement VMOVPPeter Maydell1-0/+9
2022-04-22hw/intc/arm_gicv3_its: Handle virtual interrupts in process_its_cmd()Peter Maydell1-0/+17
2022-04-22hw/intc/arm_gicv3_its: Implement VMAPPPeter Maydell1-0/+12
2022-04-22hw/intc/arm_gicv3_its: Implement VMAPI and VMAPTIPeter Maydell1-0/+9
2022-04-22hw/intc/arm_gicv3_its: Implement GITS_BASER2 for GICv4Peter Maydell1-0/+16
2022-04-22hw/intc/arm_gicv3: Report correct PIDR0 values for ID registersPeter Maydell1-2/+13
2022-02-08hw/intc/arm_gicv3_its: Fix address calculation in get_ite() and update_ite()Peter Maydell1-9/+10
2022-02-08hw/intc/arm_gicv3_its: Use address_space_map() to access command queue packetsPeter Maydell1-2/+2
2022-01-28hw/intc/arm_gicv3_its: Implement MOVIPeter Maydell1-0/+16
2022-01-28hw/intc/arm_gicv3_its: Implement MOVALLPeter Maydell1-0/+16
2022-01-28hw/intc/arm_gicv3: Set GICR_CTLR.CES if LPIs are supportedPeter Maydell1-0/+1
2022-01-28hw/intc/arm_gicv3_its: Sort ITS command list into numeric orderPeter Maydell1-5/+5
2022-01-07hw/intc/arm_gicv3_its: Use FIELD macros for CTEsPeter Maydell1-1/+2
2022-01-07hw/intc/arm_gicv3_its: Correct comment about CTE RDBase field sizePeter Maydell1-1/+1
2022-01-07hw/intc/arm_gicv3_its: Use FIELD macros for DTEsPeter Maydell1-3/+4
2022-01-07hw/intc/arm_gicv3_its: Don't misuse GITS_TYPE_PHYSICAL definePeter Maydell1-12/+14
2022-01-07hw/intc/arm_gicv3_its: Remove redundant ITS_CTLR_ENABLED definePeter Maydell1-2/+0
2021-11-26hw/intc/arm_gicv3: Add new gicv3_intid_is_special() functionPeter Maydell1-0/+13
2021-11-26hw/intc/arm_gicv3: Update cached state after LPI state changesPeter Maydell1-0/+17
2021-09-13hw/intc: GICv3 redistributor ITS processingShashi Mallela1-0/+9
2021-09-13hw/intc: GICv3 ITS Feature enablementShashi Mallela1-0/+2
2021-09-13hw/intc: GICv3 ITS Command processingShashi Mallela1-0/+12
2021-09-13hw/intc: GICv3 ITS command queue frameworkShashi Mallela1-0/+40
2021-09-13hw/intc: GICv3 ITS register definitions addedShashi Mallela1-0/+29
2021-09-13hw/intc: GICv3 ITS initial frameworkShashi Mallela1-10/+86
2017-02-28target-arm: Add GICv3CPUState in CPUARMState structVijaya Kumar K1-0/+2
2017-02-28hw/intc/arm_gicv3_kvm: Implement get/put functionsVijaya Kumar K1-0/+1
2017-01-20hw/intc/gicv3: Add defines for ICH system register fieldsPeter Maydell1-0/+79
2016-07-12Clean up decorations and whitespace around header guardsMarkus Armbruster1-1/+1
2016-06-17hw/intc/arm_gicv3: Add IRQ handling CPU interface registersPeter Maydell1-0/+5
2016-06-17hw/intc/arm_gicv3: Implement CPU i/f SGI generation registersPeter Maydell1-0/+1
2016-06-17hw/intc/arm_gicv3: Implement gicv3_cpuif_update()Peter Maydell1-4/+1
2016-06-17hw/intc/arm_gicv3: Implement GICv3 CPU interface registersPeter Maydell1-0/+1
2016-06-17hw/intc/arm_gicv3: Implement gicv3_set_irq()Peter Maydell1-0/+2
2016-06-17hw/intc/arm_gicv3: Implement GICv3 redistributor registersShlomo Pongratz1-0/+4
2016-06-17hw/intc/arm_gicv3: Implement GICv3 distributor registersShlomo Pongratz1-0/+4
2016-06-17hw/intc/arm_gicv3: Implement functions to identify next pending irqPeter Maydell1-0/+121
2016-06-17hw/intc/arm_gicv3: ARM GICv3 device frameworkShlomo Pongratz1-0/+24
2016-06-17hw/intc/arm_gicv3: Add state informationPavel Fedin1-0/+172
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