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path: root/hw/intc/armv7m_nvic.c
AgeCommit message (Expand)AuthorFilesLines
2020-03-12hw/intc/armv7m_nvic: Rebuild hflags on resetPeter Maydell1-0/+6
2020-02-28target/arm: Add isar_feature_aa32_vfp_simdRichard Henderson1-10/+10
2020-02-21target/arm: Test correct register in aa32_pan and aa32_ats1e1 checksPeter Maydell1-4/+4
2020-02-21target/arm: Define an aa32_pmu_8_1 isar feature test functionPeter Maydell1-1/+1
2020-01-24qdev: set properties with device_class_set_props()Marc-André Lureau1-1/+1
2019-10-24target/arm: Rebuild hflags for M-profile NVICRichard Henderson1-9/+13
2019-09-03memory: Access MemoryRegion with endiannessTony Nguyen1-7/+8
2019-09-03hw/intc/armv7m_nic: Access MemoryRegion with MemOpTony Nguyen1-4/+8
2019-08-16Include hw/qdev-properties.h lessMarkus Armbruster1-0/+1
2019-08-16Include migration/vmstate.h lessMarkus Armbruster1-0/+1
2019-08-16Include hw/irq.h a lot lessMarkus Armbruster1-0/+1
2019-07-04target/arm: v8M: Check state of exception being returned fromPeter Maydell1-1/+13
2019-07-04arm v8M: Forcibly clear negative-priority exceptions on deactivatePeter Maydell1-5/+35
2019-06-12Include qemu/module.h where needed, drop it from qemu-common.hMarkus Armbruster1-1/+1
2019-05-24hw/intc/nvic: Use object_initialize_child for correct reference countingPhilippe Mathieu-Daudé1-3/+3
2019-05-23arm: Remove unnecessary includes of hw/arm/arm.hPeter Maydell1-1/+0
2019-05-07hw/intc/armv7m_nvic: Don't enable ARMV7M_EXCP_DEBUG from resetPeter Maydell1-1/+3
2019-05-07hw/intc/armv7m_nvic: NS BFAR and BFSR are RAZ/WI if BFHFNMINS == 0Peter Maydell1-3/+24
2019-05-07hw/arm/armv7m_nvic: Check subpriority in nvic_recompute_state_secure()Peter Maydell1-2/+7
2019-04-29target/arm: New function armv7m_nvic_set_pending_lazyfp()Peter Maydell1-0/+96
2019-04-29target/arm: Implement v7m_update_fpccr()Peter Maydell1-0/+34
2019-04-29target/arm: Implement dummy versions of M-profile FP-related registersPeter Maydell1-0/+125
2019-04-29hw/intc/armv7m_nvic: Allow reading of M-profile MVFR* registersPeter Maydell1-0/+6
2019-02-15hw/intc/armv7m_nvic: Allow byte accesses to SHPR1Peter Maydell1-2/+2
2019-02-01armv7m: Don't assume the NVIC's CPU is CPU 0Peter Maydell1-2/+1
2018-10-24target/arm: Move some system registers into a substructureRichard Henderson1-6/+6
2018-08-20nvic: Expose NMI linePeter Maydell1-0/+19
2018-08-14nvic: Change NVIC to support ARMv6-MJulia Suvorova1-3/+18
2018-08-14arm: Add ARMv6-M programmer's model supportJulia Suvorova1-0/+10
2018-08-14nvic: Handle ARMv6-M SCS reserved registersJulia Suvorova1-2/+49
2018-07-30armv7m_nvic: Fix m-security subsection namePeter Maydell1-1/+1
2018-07-24target/arm: Escalate to correct HardFault when AIRCR.BFHFNMINS is setPeter Maydell1-2/+6
2018-07-17hw/arm/armv7: Fix crash when introspecting the "iotkit" deviceThomas Huth1-3/+2
2018-06-15arm: Don't crash if user tries to use a Cortex-M CPU without an NVICPeter Maydell1-1/+5
2018-02-15hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversionsPeter Maydell1-4/+4
2018-02-15hw/intc/armv7m_nvic: Implement SCRPeter Maydell1-4/+8
2018-02-15hw/intc/armv7m_nvic: Implement cache ID registersPeter Maydell1-0/+16
2018-02-15hw/intc/armv7m_nvic: Implement v8M CPPWR registerPeter Maydell1-0/+14
2018-02-15hw/intc/armv7m_nvic: Implement M profile cache maintenance opsPeter Maydell1-0/+12
2018-02-15hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handlingPeter Maydell1-3/+3
2018-02-15hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVICPeter Maydell1-14/+16
2018-02-09target/arm: Split "get pending exception info" from "acknowledge it"Peter Maydell1-7/+23
2018-02-09target/arm: Add armv7m_nvic_set_pending_derived()Peter Maydell1-2/+66
2018-01-16hw/intc/armv7m: Support byte and halfword accesses to CFSRPeter Maydell1-16/+22
2017-12-13nvic: Make systick bankedPeter Maydell1-13/+77
2017-12-13nvic: Make nvic_sysreg_ns_ops work with any MemoryRegionPeter Maydell1-3/+7
2017-11-20nvic: Fix ARMv7M MPU_RBAR readsPeter Maydell1-1/+1
2017-10-12nvic: Fix miscalculation of offsets into ITNS arrayPeter Maydell1-2/+2
2017-10-12nvic: Add missing 'break'Peter Maydell1-0/+1
2017-10-06nvic: Add missing code for writing SHCSR.HARDFAULTPENDED bitPeter Maydell1-0/+1
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