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path: root/hw/intc/armv7m_nvic.c
AgeCommit message (Expand)AuthorFilesLines
2019-02-01armv7m: Don't assume the NVIC's CPU is CPU 0Peter Maydell1-2/+1
2018-10-24target/arm: Move some system registers into a substructureRichard Henderson1-6/+6
2018-08-20nvic: Expose NMI linePeter Maydell1-0/+19
2018-08-14nvic: Change NVIC to support ARMv6-MJulia Suvorova1-3/+18
2018-08-14arm: Add ARMv6-M programmer's model supportJulia Suvorova1-0/+10
2018-08-14nvic: Handle ARMv6-M SCS reserved registersJulia Suvorova1-2/+49
2018-07-30armv7m_nvic: Fix m-security subsection namePeter Maydell1-1/+1
2018-07-24target/arm: Escalate to correct HardFault when AIRCR.BFHFNMINS is setPeter Maydell1-2/+6
2018-07-17hw/arm/armv7: Fix crash when introspecting the "iotkit" deviceThomas Huth1-3/+2
2018-06-15arm: Don't crash if user tries to use a Cortex-M CPU without an NVICPeter Maydell1-1/+5
2018-02-15hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversionsPeter Maydell1-4/+4
2018-02-15hw/intc/armv7m_nvic: Implement SCRPeter Maydell1-4/+8
2018-02-15hw/intc/armv7m_nvic: Implement cache ID registersPeter Maydell1-0/+16
2018-02-15hw/intc/armv7m_nvic: Implement v8M CPPWR registerPeter Maydell1-0/+14
2018-02-15hw/intc/armv7m_nvic: Implement M profile cache maintenance opsPeter Maydell1-0/+12
2018-02-15hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handlingPeter Maydell1-3/+3
2018-02-15hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVICPeter Maydell1-14/+16
2018-02-09target/arm: Split "get pending exception info" from "acknowledge it"Peter Maydell1-7/+23
2018-02-09target/arm: Add armv7m_nvic_set_pending_derived()Peter Maydell1-2/+66
2018-01-16hw/intc/armv7m: Support byte and halfword accesses to CFSRPeter Maydell1-16/+22
2017-12-13nvic: Make systick bankedPeter Maydell1-13/+77
2017-12-13nvic: Make nvic_sysreg_ns_ops work with any MemoryRegionPeter Maydell1-3/+7
2017-11-20nvic: Fix ARMv7M MPU_RBAR readsPeter Maydell1-1/+1
2017-10-12nvic: Fix miscalculation of offsets into ITNS arrayPeter Maydell1-2/+2
2017-10-12nvic: Add missing 'break'Peter Maydell1-0/+1
2017-10-06nvic: Add missing code for writing SHCSR.HARDFAULTPENDED bitPeter Maydell1-0/+1
2017-10-06nvic: Implement Security Attribution Unit registersPeter Maydell1-0/+116
2017-10-06target/arm: Add new-in-v8M SFSR and SFARPeter Maydell1-0/+34
2017-10-06target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler modePeter Maydell1-1/+1
2017-10-06nvic: Clear the vector arrays and prigroup on resetPeter Maydell1-0/+5
2017-09-21nvic: Support banked exceptions in acknowledge and completePeter Maydell1-6/+20
2017-09-21nvic: Make SHCSR banked for v8MPeter Maydell1-52/+169
2017-09-21nvic: Make ICSR banked for v8MPeter Maydell1-13/+32
2017-09-21target/arm: Handle banking in negative-execution-priority check in cpu_mmu_in...Peter Maydell1-0/+29
2017-09-21nvic: Handle v8M changes in nvic_exec_prio()Peter Maydell1-9/+42
2017-09-21nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clearPeter Maydell1-2/+10
2017-09-21nvic: Implement v8M changes to fixed priority exceptionsPeter Maydell1-3/+19
2017-09-21nvic: In escalation to HardFault, support HF not being priority -1Peter Maydell1-11/+12
2017-09-21nvic: Compare group priority for escalation to HFPeter Maydell1-1/+1
2017-09-21nvic: Make SHPR registers bankedPeter Maydell1-9/+87
2017-09-21nvic: Make set_pending and clear_pending take a secure parameterPeter Maydell1-16/+48
2017-09-21nvic: Handle banked exceptions in nvic_recompute_state()Peter Maydell1-5/+146
2017-09-21nvic: Implement NVIC_ITNS<n> registersPeter Maydell1-7/+67
2017-09-21nvic: Make ICSR.RETTOBASE handle banked exceptionsPeter Maydell1-1/+4
2017-09-21nvic: Implement AIRCR changes for v8MPeter Maydell1-11/+38
2017-09-21nvic: Add cached vectpending_prio statePeter Maydell1-10/+13
2017-09-21nvic: Add cached vectpending_is_s_banked statePeter Maydell1-0/+1
2017-09-21nvic: Add banked exception statesPeter Maydell1-1/+52
2017-09-14nvic: Don't apply group priority mask to negative prioritiesPeter Maydell1-2/+9
2017-09-07target/arm: Make CFSR register banked for v8MPeter Maydell1-2/+13
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