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path: root/hw/intc/armv7m_nvic.c
AgeCommit message (Expand)AuthorFilesLines
2017-09-21nvic: Support banked exceptions in acknowledge and completePeter Maydell1-6/+20
2017-09-21nvic: Make SHCSR banked for v8MPeter Maydell1-52/+169
2017-09-21nvic: Make ICSR banked for v8MPeter Maydell1-13/+32
2017-09-21target/arm: Handle banking in negative-execution-priority check in cpu_mmu_in...Peter Maydell1-0/+29
2017-09-21nvic: Handle v8M changes in nvic_exec_prio()Peter Maydell1-9/+42
2017-09-21nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clearPeter Maydell1-2/+10
2017-09-21nvic: Implement v8M changes to fixed priority exceptionsPeter Maydell1-3/+19
2017-09-21nvic: In escalation to HardFault, support HF not being priority -1Peter Maydell1-11/+12
2017-09-21nvic: Compare group priority for escalation to HFPeter Maydell1-1/+1
2017-09-21nvic: Make SHPR registers bankedPeter Maydell1-9/+87
2017-09-21nvic: Make set_pending and clear_pending take a secure parameterPeter Maydell1-16/+48
2017-09-21nvic: Handle banked exceptions in nvic_recompute_state()Peter Maydell1-5/+146
2017-09-21nvic: Implement NVIC_ITNS<n> registersPeter Maydell1-7/+67
2017-09-21nvic: Make ICSR.RETTOBASE handle banked exceptionsPeter Maydell1-1/+4
2017-09-21nvic: Implement AIRCR changes for v8MPeter Maydell1-11/+38
2017-09-21nvic: Add cached vectpending_prio statePeter Maydell1-10/+13
2017-09-21nvic: Add cached vectpending_is_s_banked statePeter Maydell1-0/+1
2017-09-21nvic: Add banked exception statesPeter Maydell1-1/+52
2017-09-14nvic: Don't apply group priority mask to negative prioritiesPeter Maydell1-2/+9
2017-09-07target/arm: Make CFSR register banked for v8MPeter Maydell1-2/+13
2017-09-07target/arm: Make MMFAR banked for v8MPeter Maydell1-2/+2
2017-09-07target/arm: Make CCR register banked for v8MPeter Maydell1-6/+27
2017-09-07target/arm: Make MPU_CTRL register banked for v8MPeter Maydell1-4/+5
2017-09-07target/arm: Make MPU_RNR register banked for v8MPeter Maydell1-9/+9
2017-09-07target/arm: Make MPU_RBAR, MPU_RLAR banked for v8MPeter Maydell1-4/+4
2017-09-07target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8MPeter Maydell1-4/+4
2017-09-07target/arm: Make VTOR register banked for v8MPeter Maydell1-6/+7
2017-09-07nvic: Add NS alias SCS regionPeter Maydell1-1/+65
2017-09-07target/arm: Make FAULTMASK register banked for v8MPeter Maydell1-1/+8
2017-09-07target/arm: Make PRIMASK register banked for v8MPeter Maydell1-1/+1
2017-09-07target/arm: Make BASEPRI register banked for v8MPeter Maydell1-2/+2
2017-09-07target/arm: Implement ARMv8M's PMSAv8 registersPeter Maydell1-8/+114
2017-09-04nvic: Implement "user accesses BusFault" SCS region behaviourPeter Maydell1-17/+41
2017-09-04armv7m_nvic.h: Move from include/hw/arm to include/hw/intcPeter Maydell1-1/+1
2017-09-04target/arm: Don't store M profile PRIMASK and FAULTMASK in daifPeter Maydell1-2/+2
2017-09-04hw/intc/armv7m_nvic.c: Remove out of date commentPeter Maydell1-4/+0
2017-07-31target/arm: Rename cp15.c6_rgnr to pmsav7.rnrPeter Maydell1-7/+7
2017-06-02arm: add MPU support to M profile CPUsMichael Davidsaver1-0/+104
2017-02-28armv7m: Split systick out from NVICPeter Maydell1-126/+34
2017-02-28armv7m: Make NVIC expose a memory region rather than mapping itselfPeter Maydell1-5/+2
2017-02-28armv7m: Move NVICState struct definition into headerPeter Maydell1-48/+1
2017-02-28armv7m: Allow SHCSR writes to change pending and active bitsPeter Maydell1-2/+11
2017-02-28armv7m: Check exception return consistencyPeter Maydell1-1/+11
2017-02-28armv7m: VECTCLRACTIVE and VECTRESET are UNPREDICTABLEMichael Davidsaver1-2/+6
2017-02-28armv7m: Remove unused armv7m_nvic_acknowledge_irq() return valuePeter Maydell1-3/+1
2017-02-28armv7m: Escalate exceptions to HardFault if necessaryMichael Davidsaver1-0/+53
2017-02-28armv7m: Fix condition check for taking exceptionsPeter Maydell1-0/+7
2017-02-28armv7m: Rewrite NVIC to not use any GIC codeMichael Davidsaver1-144/+594
2017-02-28armv7m: Implement reading and writing of PRIGROUPPeter Maydell1-6/+8
2017-02-28armv7m: Rename nvic_state to NVICStatePeter Maydell1-22/+22
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